A triple gate oxide CMOS technology using fluorine implant for system-on-a-chip

Abstract

We have developed a triple gate oxide CMOS technology that integrates 0.10-/spl mu/m gate length 1.2-V high-speed CMOS (tox of 1.9 nm), low-power CMOS (tox of 2.5 nm) and 2.5-V I/O transistors (tox of 5.0 nm). The key technology is fluorine implantation in order to fabricate 1.9-nm and 2.5-nm gate oxide simultaneously. We selectively implanted fluorine into low-power CMOS area and successfully reduced the gate leakage current by 1.5 orders of magnitude.