采用0.17 /spl mu/m的嵌入式DRAM技术，单元尺寸为0.23 /spl mu/m/sup 2/，采用先进的CMOS逻辑

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852771

H. Wurzer, I. Feldner, W. Graf, G. Curello, J. Faul, D. Weber, A. Kieslich

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引用次数: 0

摘要

提出了一种新的0.17 /spl mu/m嵌入式DRAM (eDRAM)技术。基于单元尺寸为0.23 /spl mu/m/sup 2/ CMOS的DRAM工艺，通过引入称为深沟隔离的新隔离概念和积极的器件缩放来改进逻辑。这是通过6级AlCu RIE金属化完成的。这一概念使单片系统(SOC)解决方案能够以最小的芯片尺寸和最高的成品率实现高达数百Mbits的DRAM容量。

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A 0.17 /spl mu/m embedded DRAM technology with 0.23 /spl mu/m/sup 2/ cell size and advanced CMOS logic

A new 0.17 /spl mu/m embedded DRAM (eDRAM) technology is presented. Basing on a DRAM process with a cell size of 0.23 /spl mu/m/sup 2/ CMOS logic has been improved by introducing a new isolation concept called deep trench isolation and an aggressive device scaling. This is completed by a 6-level AlCu RIE metalization. This concept enables a system-on-a-chip (SOC) solution up to several hundred Mbits DRAM capacity on smallest chip size and highest yield perspectives.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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