SiGe heterojunctions in epitaxial vertical surrounding-gate MOSFETs

Abstract

Vertical MOSFETs are possible future architectures for memory cells as well as alternatives for conventional CMOS devices. The vertical channel allows growth of epitaxial structures, such as heterostructures, before the pillars are etched. We show how incorporation of SiGe heterostructures in vertical MOSFET devices can be used to delay the floating body effect or to modify hot carrier characteristics.