嵌入式DRAM低温(<500/spl℃)SrTiO/sub - 3/电容器工艺技术

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852787

J. Nakahira, M. Kiyotoshi, S. Yamazaki, M. Nakabayashi, S. Niwa, K. Tsunoda, J. Lin, A. Shimada, M. Izuha, T. Aoyama, H. Tomita, K. Eguchi, K. Hieda

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引用次数: 1

摘要

我们开发了用于嵌入式DRAM的低温SrTiO/sub 3/ (ST)电容器工艺。在475/spl℃下沉积的ST薄膜无需额外退火即可结晶。得到了0.53nm SiO/sub 2/等效厚度(teq)的Ru电极ST电容器。采用低温ST工艺制备的256K三维电容器在/spl plusmn/0.8V时，凹形结构电容器的漏电流小于1fA/cell。ST电容器工艺可以满足较低的加工温度和可扩展到极薄介质层和低泄漏电流的要求。

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Low temperature (<500/spl deg/C) SrTiO/sub 3/ capacitor process technology for embedded DRAM

We have developed low temperature SrTiO/sub 3/ (ST) capacitor process for embedded DRAM. ST film deposited at 475/spl deg/C was crystallized without additional annealing. 0.53nm SiO/sub 2/ equivalent thickness (teq) ST capacitor with Ru electrodes was obtained. The leakage current of the concave structure capacitor was less than 1fA/cell at /spl plusmn/0.8V for 256K 3-dimensional (3D) capacitors fabricated by the low temperature ST process. ST capacitor process can satisfy demands on lower processing temperature and scalability to very thin dielectric layer with low leakage current.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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