低偏置等离子体掺杂可提高0.1 /spl μ m以下pmosfet的性能

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852789

D. Lenoble, F. Arnaud, A. Grouillet, R. Liebert, S. Walther, S. Felch, Z. Fangi, M. Haond

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引用次数: 6

摘要

我们首次将低偏置等离子体掺杂(LB PLAD)技术用于扩展掺杂在工业0.13 /spl mu/m CMOS工艺中。与超低能离子注入(B/sup +/和BF/sub 2//sup +/)技术(ULE I/I)相比，等离子体掺杂器件表现出更好的短通道效应(SCE)和亚阈值性能，这主要归功于良好的结特性(权衡结深度(X/sub j/)/片电阻(R/sub s/))。

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Reliable and enhanced performances of sub-0.1 /spl mu/m pMOSFETs doped by low biased plasma doping

For the first time, we include low biased plasma doping (LB PLAD) technique for extensions doping within an industrial 0.13 /spl mu/m CMOS process. By comparing to the Ultra-Low Energy Ion Implantation (B/sup +/ and BF/sub 2//sup +/) technique (ULE I/I), plasma doped devices exhibits improved Short Channel Effect (SCE) and subthreshold performances mostly attributed to the good junction characteristics (tradeoff junction depth (X/sub j/)/sheet resistance (R/sub s/)).

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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