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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)最新文献

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Quantitative yield and reliability projection from antenna test results-a case study 天线试验结果的定量良率和可靠性预测——一个案例研究
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852784
P. Mason, K.P. Cheung, D. Hwang, M. Creusen, R. Degraeve, B. Kaczer
{"title":"Quantitative yield and reliability projection from antenna test results-a case study","authors":"P. Mason, K.P. Cheung, D. Hwang, M. Creusen, R. Degraeve, B. Kaczer","doi":"10.1109/VLSIT.2000.852784","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852784","url":null,"abstract":"To monitor plasma charging damage, it is common to use extremely large antenna ratio (AR) testers to improve sensitivity. Calculating how the measured damage to these large AR testers impacts product is a serious issue that has not yet been resolved. Without the ability to predict the damage impact to product, and hence to quantitatively establish antenna design rules, the only way to ensure product reliability is to reduce damage as best we can and to use tight design rules. Such practice is extremely costly and provides no assurance. The purpose of this paper is to illustrate a quantitative methodology to deal with the above-mentioned problem using a real example.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133822421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Vdd impact on propagation pulse width variation in PD SOI circuits Vdd对PD SOI电路中传播脉宽变化的影响
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852825
B. Min, G. Workman, D. Chang, O. Zia, Y. Yu, R. Widenhofer, B. Simon, N. Cave, H. Sanchez, S. Veeraraghavan, M. Mendicino, B. Yeargain
{"title":"Vdd impact on propagation pulse width variation in PD SOI circuits","authors":"B. Min, G. Workman, D. Chang, O. Zia, Y. Yu, R. Widenhofer, B. Simon, N. Cave, H. Sanchez, S. Veeraraghavan, M. Mendicino, B. Yeargain","doi":"10.1109/VLSIT.2000.852825","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852825","url":null,"abstract":"Pulse width variation through open-ended chains in partially depleted SOI is investigated. Vdd impact on the pulse variation (either compression or stretching) is intensively studied, as well as temperature and illumination contributions. A physical model using well-known capacitive coupling, generation, and recombination concepts is proposed with experimental data.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124208312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mass-productive high performance 0.5 /spl mu/m embedded FRAM technology with triple layer metal 量产高性能0.5 /spl mu/m的三层金属嵌入式FRAM技术
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852757
A. Itoh, Y. Hikosaka, T. Saito, H. Naganuma, H. Miyazawa, Y. Ozaki, Y. Kato, S. Mihara, H. Iwamoto, S. Mochizuki, M. Nakamura, T. Yamazaki
{"title":"Mass-productive high performance 0.5 /spl mu/m embedded FRAM technology with triple layer metal","authors":"A. Itoh, Y. Hikosaka, T. Saito, H. Naganuma, H. Miyazawa, Y. Ozaki, Y. Kato, S. Mihara, H. Iwamoto, S. Mochizuki, M. Nakamura, T. Yamazaki","doi":"10.1109/VLSIT.2000.852757","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852757","url":null,"abstract":"Mass-productive 0.5 /spl mu/m embedded FRAM with triple layer metal (one local interconnect and two Aluminum interconnects) has been developed. Fabrication processes are fully compatible with high-end logic LSIs using W-CVD via filling process. Using the high performance PZT capacitor and optimized metallization processes, we achieved high retention reliability even after triple layer metal process.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124417148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Sub-0.1 /spl mu/m CMOS with source/drain extension spacer formed using nitrogen implantation prior to thick gate re-oxidation 低于0.1 /spl μ l /m的CMOS，源/漏扩展间隔层在厚栅再氧化之前通过氮注入形成
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852820
J.C. Hu, A. Chatterjee, M. Mehrotra, J. Xu, W. Shiau, M. Rodder
{"title":"Sub-0.1 /spl mu/m CMOS with source/drain extension spacer formed using nitrogen implantation prior to thick gate re-oxidation","authors":"J.C. Hu, A. Chatterjee, M. Mehrotra, J. Xu, W. Shiau, M. Rodder","doi":"10.1109/VLSIT.2000.852820","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852820","url":null,"abstract":"Source/drain (S/D) extensions with low R/sub s/ and low C/sub gd/ are required for high performance CMOS. In this work, we report on a new process whereby an extension spacer is formed after gate etch using a blanket nitrogen ion implantation (N I/I) prior to thick gate reoxidation (GROX). The new process reduces n, pMOS C/sub gd/ by 12% and 20%, respectively and nMOS C/sub gate/ by 10%, compared to a conventional device, while maintaining high I/sub drive/. The nitrogen retards formation of a thick oxide on active regions allowing for a well controlled low energy extension implant, even with a thick gate re-ox spacer. The impact of nitrogen introduced after gate-etch but before the GROX on devices is also described for the first time.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129113803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.99-/spl mu/m/sup 2/ loadless four-transistor SRAM cell in 0.13-/spl mu/m generation CMOS technology 一个0.99-/spl mu/m/sup 2/无负载四晶体管SRAM单元采用0.13-/spl mu/m一代CMOS技术
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852810
S. Masuoka, K. Noda, S. Ito, K. Matsui, K. Imai, N. Yasuzato, H. Kawamoto, N. Ikezawa, K. Ando, S. Koyama, T. Tamura, Y. Yamada, T. Horiuchi
{"title":"A 0.99-/spl mu/m/sup 2/ loadless four-transistor SRAM cell in 0.13-/spl mu/m generation CMOS technology","authors":"S. Masuoka, K. Noda, S. Ito, K. Matsui, K. Imai, N. Yasuzato, H. Kawamoto, N. Ikezawa, K. Ando, S. Koyama, T. Tamura, Y. Yamada, T. Horiuchi","doi":"10.1109/VLSIT.2000.852810","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852810","url":null,"abstract":"Summary form only given. We present an ultra-high-density embedded loadless four-transistor SRAM cell for 0.13-/spl mu/m logic LSIs. The cell size is 0.99 /spl mu/m/sup 2/, which is the smallest of all reported SRAM cells. In addition, its fabrication process is fully compatible with CMOS logic technologies. The following three technologies reduce the cell area to less than 1 /spl mu/m/sup 2/, and provide highly stable operation at 1.2 V. The double-exposure technique using KrF excimer laser lithography with complementary phase-shift masks reduces the spacing between the drive-transistor gate and the word line. Using the borderless-contact etching process expands shared contact up to 0.21 /spl mu/m without contact leakage current to obtain sufficient misalignment tolerance. The thickness of the gate dielectrics in the cell is controlled to suppress the direct tunneling current to less than the off-state current in order to retain the cell data from -40 to 125/spl deg/C.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115232304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Impact of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications 采用高电阻率衬底混合沟槽隔离的0.18 /spl mu/m SOI CMOS技术对嵌入式RF/模拟应用的影响
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852806
S. Maeda, Y. Wada, K. Yamamoto, H. Komurasaki, T. Matsumoto, Y. Hirano, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, M. Inuishi
{"title":"Impact of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications","authors":"S. Maeda, Y. Wada, K. Yamamoto, H. Komurasaki, T. Matsumoto, Y. Hirano, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, M. Inuishi","doi":"10.1109/VLSIT.2000.852806","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852806","url":null,"abstract":"In this paper, for the first time, we propose a 0.18/spl mu/m SOI CMOS using hybrid trench isolation with high resistivity substrates (HRS) and reveal its impact on high performance embedded RF/analog applications, which is essential for \"system on a chip (SOC)\". The hybrid trench isolation is a type of partial trench isolation which serves scalable body-tied SOI MOSFETs, and full trench isolation which provides high quality passives associated with the HRS. Using this technology, the advantages of SOI MOSFETs are quantitatively proven. Excellent body-fixing capability of this SOI MOSFET, and high-quality on-chip inductance is demonstrated for RF/analog LSIs. For mixed-signal configurations, superior CMOS performance is demonstrated.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116216993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CMOS with active well bias for low-power and RF/analog applications 具有有源偏置的CMOS，适用于低功耗和RF/模拟应用
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852808
C. Wann, J. Harrington, R. Mih, S. Biesemans, K. Han, R. Dennard, O. Prigge, Chuan Lin, R. Mahnkopf, Bomy A. Chen
{"title":"CMOS with active well bias for low-power and RF/analog applications","authors":"C. Wann, J. Harrington, R. Mih, S. Biesemans, K. Han, R. Dennard, O. Prigge, Chuan Lin, R. Mahnkopf, Bomy A. Chen","doi":"10.1109/VLSIT.2000.852808","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852808","url":null,"abstract":"We show that with a forward body bias, CMOS performance can be improved for those applications which are primarily concerned with speed, and for those which have fixed performance targets but desire lower switching energy (higher MHz/mW). Thus V/sub t/ can be set according to standby power requirement or device design (well and halo engineering), forward body bias is then applied to improve speed or to reduce active power. No compromise in I/sub off/ results if the forward bias is applied when the circuits are active, during which time I/sub off/ and the leakage current are small compared to the switching current. Therefore a low-power CMOS strategy should use a MOSFET as a four-terminal device with a fast top gate and a slow bottom gate shared by a block. Deep-trench isolation with STI provides fine-grain isolation for body bias blocks without area penalty. Making the body available also improves the device analog properties and enables new applications. We present an active-well VCO/mixer as an example.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124319532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Single-layer thin HfO/sub 2/ gate dielectric with n+-polysilicon gate 具有n+-多晶硅栅极的单层薄HfO/sub /栅极电介质
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852762
L. Kang, Y. Jeon, K. Onishi, B. Lee, W. Qi, R. Nieh, S. Gopalan, J.C. Lee
{"title":"Single-layer thin HfO/sub 2/ gate dielectric with n+-polysilicon gate","authors":"L. Kang, Y. Jeon, K. Onishi, B. Lee, W. Qi, R. Nieh, S. Gopalan, J.C. Lee","doi":"10.1109/VLSIT.2000.852762","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852762","url":null,"abstract":"MOSCAPs and MOSFETs of a single-layer thin HfO/sub 2/ gate dielectric with n+ polysilicon gate were fabricated and characterized. Polysilicon process was optimized such that leakage current and equivalent oxide thickness of HfO/sub 2/ remained low. Excellent C-V properties (e.g. low Dit and frequency dispersion) and reliability characteristics were obtained. Reasonable MOSFET quality was also demonstrated.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"344 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123314495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Performance of MOSFETs with ultra thin ZrO/sub 2/ and Zr silicate gate dielectrics 超薄ZrO/sub /和Zr硅酸盐栅极电介质mosfet的性能
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852760
W. Qi, R. Nieh, B. Lee, K. Onishi, L. Kang, Y. Jeon, Jack C. Lee, V. Kaushik, '. Bich-YenNeuyen, '. LataPrabhu, K. Eisenbeiser, J. Finder
{"title":"Performance of MOSFETs with ultra thin ZrO/sub 2/ and Zr silicate gate dielectrics","authors":"W. Qi, R. Nieh, B. Lee, K. Onishi, L. Kang, Y. Jeon, Jack C. Lee, V. Kaushik, '. Bich-YenNeuyen, '. LataPrabhu, K. Eisenbeiser, J. Finder","doi":"10.1109/VLSIT.2000.852760","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852760","url":null,"abstract":"In this paper, we report the transistor performance of both PMOS and NMOS fabricated with ZrO/sub 2/ and Zr-silicate gate dielectrics. These high-k films exhibit low leakage, low subthreshold swing (S), and good on-off characteristics. Good effective electron and hole mobilities were obtained. It was found that for Zr-silicate, a mobility closer to thermal SiO/sub 2/ was demonstrated due to the better interface with Si substrate.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126450201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Advanced shallow trench isolation to suppress the inverse narrow channel effects for 0.24 /spl mu/m pitch isolation and beyond 先进的浅沟隔离抑制0.24 /spl亩/米间距隔离及以上的反向窄通道效应
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852816
K. Horita, T. Kuroi, Y. Itoh, K. Shiozawa, K. Eikyu, K. Goto, Y. Inoue, M. Inuishi
{"title":"Advanced shallow trench isolation to suppress the inverse narrow channel effects for 0.24 /spl mu/m pitch isolation and beyond","authors":"K. Horita, T. Kuroi, Y. Itoh, K. Shiozawa, K. Eikyu, K. Goto, Y. Inoue, M. Inuishi","doi":"10.1109/VLSIT.2000.852816","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852816","url":null,"abstract":"A novel shallow trench isolation (STI) technique named Poly-Si-Buffered-mask STI (PB-STI) using the SiN/poly-Si/SiO/sub 2/ stacked mask has been proposed. The poly-Si is oxidized at the step of liner oxidation and then a \"small bird's beak\" is grown. With small bird's beak formation the oxide recess at the trench edge is prevented and the fringing of electric-field from the gate electrode can be effectively avoided. PB-STI can completely suppress the inverse narrow channel effect with quite simple process sequence which includes no corner implantation.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131815555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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