Impact of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

Abstract

In this paper, for the first time, we propose a 0.18/spl mu/m SOI CMOS using hybrid trench isolation with high resistivity substrates (HRS) and reveal its impact on high performance embedded RF/analog applications, which is essential for "system on a chip (SOC)". The hybrid trench isolation is a type of partial trench isolation which serves scalable body-tied SOI MOSFETs, and full trench isolation which provides high quality passives associated with the HRS. Using this technology, the advantages of SOI MOSFETs are quantitatively proven. Excellent body-fixing capability of this SOI MOSFET, and high-quality on-chip inductance is demonstrated for RF/analog LSIs. For mixed-signal configurations, superior CMOS performance is demonstrated.