A. Itoh, Y. Hikosaka, T. Saito, H. Naganuma, H. Miyazawa, Y. Ozaki, Y. Kato, S. Mihara, H. Iwamoto, S. Mochizuki, M. Nakamura, T. Yamazaki
{"title":"量产高性能0.5 /spl mu/m的三层金属嵌入式FRAM技术","authors":"A. Itoh, Y. Hikosaka, T. Saito, H. Naganuma, H. Miyazawa, Y. Ozaki, Y. Kato, S. Mihara, H. Iwamoto, S. Mochizuki, M. Nakamura, T. Yamazaki","doi":"10.1109/VLSIT.2000.852757","DOIUrl":null,"url":null,"abstract":"Mass-productive 0.5 /spl mu/m embedded FRAM with triple layer metal (one local interconnect and two Aluminum interconnects) has been developed. Fabrication processes are fully compatible with high-end logic LSIs using W-CVD via filling process. Using the high performance PZT capacitor and optimized metallization processes, we achieved high retention reliability even after triple layer metal process.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Mass-productive high performance 0.5 /spl mu/m embedded FRAM technology with triple layer metal\",\"authors\":\"A. Itoh, Y. Hikosaka, T. Saito, H. Naganuma, H. Miyazawa, Y. Ozaki, Y. Kato, S. Mihara, H. Iwamoto, S. Mochizuki, M. Nakamura, T. Yamazaki\",\"doi\":\"10.1109/VLSIT.2000.852757\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Mass-productive 0.5 /spl mu/m embedded FRAM with triple layer metal (one local interconnect and two Aluminum interconnects) has been developed. Fabrication processes are fully compatible with high-end logic LSIs using W-CVD via filling process. Using the high performance PZT capacitor and optimized metallization processes, we achieved high retention reliability even after triple layer metal process.\",\"PeriodicalId\":268624,\"journal\":{\"name\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2000.852757\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2000.852757","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Mass-productive high performance 0.5 /spl mu/m embedded FRAM technology with triple layer metal
Mass-productive 0.5 /spl mu/m embedded FRAM with triple layer metal (one local interconnect and two Aluminum interconnects) has been developed. Fabrication processes are fully compatible with high-end logic LSIs using W-CVD via filling process. Using the high performance PZT capacitor and optimized metallization processes, we achieved high retention reliability even after triple layer metal process.
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