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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)最新文献

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Making 50 nm transistors with 248 nm lithography 用248nm光刻技术制造50nm晶体管
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852766
P. Stolk, P. Dirksen, C. Juffermans, R. Roes, A. Montree, J. van Wingerden, W.J.M. de Laat, Wendy F. Gehoel-van Ansem, M. Kaiser, J. Kwinten, C. van der Poel
{"title":"Making 50 nm transistors with 248 nm lithography","authors":"P. Stolk, P. Dirksen, C. Juffermans, R. Roes, A. Montree, J. van Wingerden, W.J.M. de Laat, Wendy F. Gehoel-van Ansem, M. Kaiser, J. Kwinten, C. van der Poel","doi":"10.1109/VLSIT.2000.852766","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852766","url":null,"abstract":"Using a novel phase-shift mask, 50 nm resolution has been achieved with conventional 248 nm lithography. The addition of so-called scattering bars enables within-die control of linewidths from 250 to 50 nm. Using 200 nm thick resist layers combined with hard mask processing, transistors with gate-lengths down to 50 nm have been fabricated. Well controlled device performance is achieved by optimizing offset spacers and pocket implants.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133125416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A flash EEPROM cell with self-aligned trench transistor and isolation structure 一种具有自对准沟槽晶体管和隔离结构的闪存EEPROM单元
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852795
K. Nakagawa, K. Yoshida, S. Masuda, A. Yoshino, I. Sakai
{"title":"A flash EEPROM cell with self-aligned trench transistor and isolation structure","authors":"K. Nakagawa, K. Yoshida, S. Masuda, A. Yoshino, I. Sakai","doi":"10.1109/VLSIT.2000.852795","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852795","url":null,"abstract":"For future high-density contactless-NOR-type flash EEPROMs, a new memory cell with self-aligned trench transistor and isolation structure has been proposed, and its feasibility was demonstrated. The short channel effect was suppressed markedly down to the feature size (F) of 0.14 /spl mu/m with the tunnel oxide thickness of 9 nm, and excellent endurance performance (>10/sup 5/ Fowler-Nordheim write/erase cycles) of the memory cell with the area of 0.16 /spl mu/m/sup 2/ (8F/sup 2/, F=0.14 /spl mu/m) was realized.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115040813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An accurate non-quasistatic MOSFET model for simulation of RF and high speed circuits 一个精确的非准静态MOSFET模型，用于射频和高速电路的仿真
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852823
Xiaodong Jin, K. Cao, J. Ou, Weidong Liu, Yuhua Cheng, M. Matloubian, C. Hu
{"title":"An accurate non-quasistatic MOSFET model for simulation of RF and high speed circuits","authors":"Xiaodong Jin, K. Cao, J. Ou, Weidong Liu, Yuhua Cheng, M. Matloubian, C. Hu","doi":"10.1109/VLSIT.2000.852823","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852823","url":null,"abstract":"An accurate Non-Quasistatic SPICE model based on relaxation time is proposed for ac and transient simulation of high speed and radio frequency (RF) circuits. A method for extracting the relaxation time is also provided. Its dependence on Vgs and Vds and channel length is based on physics and built in the model. Finally the model is verified with both 2D simulation and measurement.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114373380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A CMOS technology platform for 0.13 /spl mu/m generation SOC (system on a chip) 0.13 /spl mu/m一代SOC(片上系统)的CMOS技术平台
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852802
H. Yoshimura, T. Nakayama, M. Nishigohri, M. Inohara, K. Miyashita, E. Morifuji, A. Oishi, H. Kawashima, M. Habu, H. Koike, H. Takato, Y. Toyoshima, H. Ishiuchi
{"title":"A CMOS technology platform for 0.13 /spl mu/m generation SOC (system on a chip)","authors":"H. Yoshimura, T. Nakayama, M. Nishigohri, M. Inohara, K. Miyashita, E. Morifuji, A. Oishi, H. Kawashima, M. Habu, H. Koike, H. Takato, Y. Toyoshima, H. Ishiuchi","doi":"10.1109/VLSIT.2000.852802","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852802","url":null,"abstract":"In this paper, we demonstrate a platform technology for 0.13 /spl mu/m generation SOC (system on a chip). 0.11 /spl mu/m LOGIC process with trench capacitor DRAM cell of 0.3 /spl mu/m/sup 2/ and 6Tr SRAM cell of 2.5 /spl mu/m/sup 2/ is described. Source/drain extensions are formed after deep junction activation by using disposable gate sidewalls. Thus ideal annealing condition is applied to source/drain extensions for shallow junction formation. In addition, second sidewalls for Co salicide are optimized for suppression of boron penetration from p/sup +/ poly-silicon gate.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116742547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A simple embedded DRAM process for 0.16-/spl mu/m CMOS technologies 用于0.16-/spl mu/m CMOS技术的简单嵌入式DRAM工艺
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852769
C. Liu, P.W. Diodato, S. Rogers, W. Lai, C. Chen, E. J. Lloyd, C.Y. Sun, D. Barr, R. Liu, C. Chang, L. Trimble, C. Pai, H. Vaidya
{"title":"A simple embedded DRAM process for 0.16-/spl mu/m CMOS technologies","authors":"C. Liu, P.W. Diodato, S. Rogers, W. Lai, C. Chen, E. J. Lloyd, C.Y. Sun, D. Barr, R. Liu, C. Chang, L. Trimble, C. Pai, H. Vaidya","doi":"10.1109/VLSIT.2000.852769","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852769","url":null,"abstract":"A simple embedded DRAM (eDRAM) process that minimizes the front-end add-on cost is presented for 0.16-/spl mu/m CMOS technologies. The structure results in a low-leakage device (<20 fA/cell at 100/spl deg/C) suitable for future generations of eDRAMs. Without using poly-Si plugs or metal-0 bit-line runners, topography is identical to the core LOGIC process. Low-temperature MIM capacitors are easily integrated using the W-plugs of metal-2 level. The number of total additional lithographic steps is only 3-5.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116165564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel logic compatible gain cell with two transistors and one capacitor 一种具有两个晶体管和一个电容的新型逻辑兼容增益单元
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852812
N. Ikeda, T. Terano, H. Moriya, T. Emori, T. Kobayashi
{"title":"A novel logic compatible gain cell with two transistors and one capacitor","authors":"N. Ikeda, T. Terano, H. Moriya, T. Emori, T. Kobayashi","doi":"10.1109/VLSIT.2000.852812","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852812","url":null,"abstract":"Summary form only given. In consumer electronics, cost-effective embedded technology is an important subject. We propose a novel, cost-effective gain cell for memory embedded in logic LSIs. The new cell consists of two conventional bulk transistors and one MOS capacitor. It can be fabricated using the pure logic process with a few additional process steps. The fabrication cost of this cell is lower than that of DRAM or SRAM at a memory density in the 1/spl sim/100 Mbit range.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122279301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs 0.13 /spl mu/m DRAM技术，适用于千兆比特密度的单机和嵌入式DRAM
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852748
K.N. Kim, T. Chung, H. Jeong, J. Moon, Y.W. Park, G. Jeong, K. Lee, G. Koh, D.W. Shin, Y. Hwang, D. Kwak, H. Uh, D. Ha, J. Lee, S. Shin, M. Lee, Y. Chun, J.K. Lee, B.J. Park, J. Oh, J.G. Lee, S. Lee
{"title":"A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs","authors":"K.N. Kim, T. Chung, H. Jeong, J. Moon, Y.W. Park, G. Jeong, K. Lee, G. Koh, D.W. Shin, Y. Hwang, D. Kwak, H. Uh, D. Ha, J. Lee, S. Shin, M. Lee, Y. Chun, J.K. Lee, B.J. Park, J. Oh, J.G. Lee, S. Lee","doi":"10.1109/VLSIT.2000.852748","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852748","url":null,"abstract":"In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126808156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A partially-depleted SOI compact model - formulation and parameter extraction 部分耗尽SOI紧凑模型的建立与参数提取
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852827
S. Fung, L. Wagner, M. Sherony, N. Zamdmer, J. Sleight, M. Michel, E. Leobandung, S.-H. Lo, T. Chen, F. Assaderaghi
{"title":"A partially-depleted SOI compact model - formulation and parameter extraction","authors":"S. Fung, L. Wagner, M. Sherony, N. Zamdmer, J. Sleight, M. Michel, E. Leobandung, S.-H. Lo, T. Chen, F. Assaderaghi","doi":"10.1109/VLSIT.2000.852827","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852827","url":null,"abstract":"As SOI technology advances into mainstream, an accurate and predictive compact model is necessary to ensure the success of VLSI chip design. This paper describes a compact model which contributes to the successful implementation of the sophisticated 660 MHz 64-bit PowerPC at its first design. This model captures all important SOI specific device characteristics and circuit behavior properly. The parameter extraction methodology, which is essential in achieving a highly accurate model, will be discussed. Verification results using a 0.18 um (1.5 V) high performance SOI CMOS technology will be presented.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127509987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Scaling guideline of DRAM memory cells for maintaining the retention time 维持保持时间的DRAM存储单元的缩放指南
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852779
S. Ueno, Y. Inoue, M. Inuishi
{"title":"Scaling guideline of DRAM memory cells for maintaining the retention time","authors":"S. Ueno, Y. Inoue, M. Inuishi","doi":"10.1109/VLSIT.2000.852779","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852779","url":null,"abstract":"We propose the model of junction leakage current of local cells. Our model can well explain voltage, temperature dependence and distribution of the leakage current. This model indicates that interface state is considered to control the leakage current and retention time. Based on our model, we found that decreasing the trap density and the electric field are effective for decreasing the leakage current. Moreover, a guideline of trap density, storage capacitance and electric field is proposed for designing future DRAMs to maintain the retention time.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126975406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Impact of ion implantation statistics on V/sub T/ fluctuations in MOSFETs: comparison between decaborane and boron channel implants 离子注入统计对mosfet中V/sub T/波动的影响:十硼烷和硼通道植入的比较
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852799
H. Tuinhout, F. Widdershoven, P. Stolk, J. Schmitz, B. Dirks, K. van der Tak, P. Bancken, J. Politiek
{"title":"Impact of ion implantation statistics on V/sub T/ fluctuations in MOSFETs: comparison between decaborane and boron channel implants","authors":"H. Tuinhout, F. Widdershoven, P. Stolk, J. Schmitz, B. Dirks, K. van der Tak, P. Bancken, J. Politiek","doi":"10.1109/VLSIT.2000.852799","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852799","url":null,"abstract":"MOSFETs with virtually identical doping profiles and DC behaviour exhibit significantly larger stochastic threshold voltage fluctuations when the channel is implanted using decaborane (B/sub 10/H/sub 14/) as compared to those with conventional boron implanted channels. This paper presents a unique experimental confirmation of the contribution of ion implantation statistics to V/sub T/ fluctuations.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134152199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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