A simple embedded DRAM process for 0.16-/spl mu/m CMOS technologies

Abstract

A simple embedded DRAM (eDRAM) process that minimizes the front-end add-on cost is presented for 0.16-/spl mu/m CMOS technologies. The structure results in a low-leakage device (<20 fA/cell at 100/spl deg/C) suitable for future generations of eDRAMs. Without using poly-Si plugs or metal-0 bit-line runners, topography is identical to the core LOGIC process. Low-temperature MIM capacitors are easily integrated using the W-plugs of metal-2 level. The number of total additional lithographic steps is only 3-5.