A CMOS technology platform for 0.13 /spl mu/m generation SOC (system on a chip)

Abstract

In this paper, we demonstrate a platform technology for 0.13 /spl mu/m generation SOC (system on a chip). 0.11 /spl mu/m LOGIC process with trench capacitor DRAM cell of 0.3 /spl mu/m/sup 2/ and 6Tr SRAM cell of 2.5 /spl mu/m/sup 2/ is described. Source/drain extensions are formed after deep junction activation by using disposable gate sidewalls. Thus ideal annealing condition is applied to source/drain extensions for shallow junction formation. In addition, second sidewalls for Co salicide are optimized for suppression of boron penetration from p/sup +/ poly-silicon gate.