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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)最新文献

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A thin amorphous silicon buffer process for suppression of W polymetal gate depletion in PMOS 一种抑制PMOS中W多金属栅损耗的非晶硅薄缓冲工艺
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852775
F. Ohtake, Y. Akasaka, A. Murakoshi, K. Suguro, T. Nakanishi
{"title":"A thin amorphous silicon buffer process for suppression of W polymetal gate depletion in PMOS","authors":"F. Ohtake, Y. Akasaka, A. Murakoshi, K. Suguro, T. Nakanishi","doi":"10.1109/VLSIT.2000.852775","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852775","url":null,"abstract":"The mechanism of gate depletion in PMOS W polymetal (W/WN/sub x//poly-Si) gate was investigated. It was found for the first time that the pile-up of boron (B) occurred at the WN/sub x//poly-Si interface due to B-N formation and the B concentration in poly-Si decreased resulting in gate depletion. In order to prevent the B pile-up, we developed a new process module and succeeded in suppressing the gate depletion without B penetration into Si substrate by using a thin amorphous Si buffer (ASB) layer combined with miniaturization of poly-Si grain-size.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130205347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High quality La/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/ gate dielectrics with equivalent oxide thickness 5-10 /spl Aring/ 高品质的La/sub 2/O/sub 3/和Al/sub 2/O/sub 3/栅极电介质，等效氧化厚度为5-10 /spl
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852751
A. Chin, Y.H. Wu, S.B. Chen, C. Liao, W. Chen
{"title":"High quality La/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/ gate dielectrics with equivalent oxide thickness 5-10 /spl Aring/","authors":"A. Chin, Y.H. Wu, S.B. Chen, C. Liao, W. Chen","doi":"10.1109/VLSIT.2000.852751","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852751","url":null,"abstract":"High quality La/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/ are fabricated with EOT of 4.8 and 9.6 /spl Aring/, leakage current of 0.06 and 0.4 A/cm/sup -2/ and D/sub it/ of both 3/spl times/10/sup 10/ eV/sup -1//cm/sup 2/, respectively. The high K is further evidenced from high MOSFET's I/sub d/ and g/sub m/ with low I/sub OFF/. Good SILC and Q/sub BD/ are obtained and comparable with SiO/sub 2/. The low EOT is due to the high thermodynamic stability in contact with Si and stable after H/sub 2/ annealing up to 550/spl deg/C.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"28 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132972761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
A 0.135 /spl mu/m/sup 2/ 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM 一个0.135 /spl mu/m/sup 2/ 6F/sup 2/沟槽侧壁垂直器件单元，用于4gb / 16gb DRAM
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852777
C. Radens, U. Gruening, J. Mandelman, M. Seitz, D. Lea, D. Casarotto, L. Clevenger, L. Nesbit, R. Malik, S. Halle, S. Kudelka, H. Tews, R. Divakaruni, J. Sim, A. Strong, D. Tibbel, N. Arnold, S. Bukofsky, J. Preuninger, G. Kunkel, G. Bronner
{"title":"A 0.135 /spl mu/m/sup 2/ 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM","authors":"C. Radens, U. Gruening, J. Mandelman, M. Seitz, D. Lea, D. Casarotto, L. Clevenger, L. Nesbit, R. Malik, S. Halle, S. Kudelka, H. Tews, R. Divakaruni, J. Sim, A. Strong, D. Tibbel, N. Arnold, S. Bukofsky, J. Preuninger, G. Kunkel, G. Bronner","doi":"10.1109/VLSIT.2000.852777","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852777","url":null,"abstract":"A 0.135 /spl mu/m/sup 2/ trench-capacitor DRAM cell with a trench-sidewall vertical-channel array device has been fabricated using 150 nm groundrules and optical lithography. This 6F/sup 2/ cell features a novel active area layout, a trench-top-oxide (TTO) isolation between trench capacitor and trench gate, maskless self-aligned buried strap node contact, shallow trench isolation (STI), a self-aligned poly-plug bit contact, and two levels of bitline interconnect, both formed using a W dual-damascene process.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131106748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High density embedded DRAM technology with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization 采用W/多晶硅栅极和Cu双金属化技术，实现了DRAM节距为0.38 /spl μ m, LOGIC节距为0.42 /spl μ m的高密度嵌入式DRAM技术
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852770
N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi, T. Oashi, K. Tsukamoto, S. Komori, K. Tomita, T. Inbe, R. Ohsaki, T. Hanawa, S. Sakamori, M. Shirahata, J. Tsuchimoto, T. Eimori
{"title":"High density embedded DRAM technology with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization","authors":"N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi, T. Oashi, K. Tsukamoto, S. Komori, K. Tomita, T. Inbe, R. Ohsaki, T. Hanawa, S. Sakamori, M. Shirahata, J. Tsuchimoto, T. Eimori","doi":"10.1109/VLSIT.2000.852770","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852770","url":null,"abstract":"A high density Embedded DRAM technology has been developed with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC/SRAM. This technology includes (1)W/WNx polymetal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-plugged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology realizes both very small. DRAM cell size of 0.29 /spl mu/m SRAM cell size of 2.77 /spl mu/m/sup 2/ on the same die.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132047294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
New frontiers of sub-100 nm VLSI technology-moving toward device and circuit co-design 100纳米以下超大规模集成电路技术的新前沿——器件与电路协同设计
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852746
M. Fukuma
{"title":"New frontiers of sub-100 nm VLSI technology-moving toward device and circuit co-design","authors":"M. Fukuma","doi":"10.1109/VLSIT.2000.852746","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852746","url":null,"abstract":"Scaling has been a basic principle for continuing progress in the development of VLSIs for a long time. However, this situation is changing when the design rule is approaching to 100 nm or less, and the SOC has become important. Instead of conventional scaling, integration of digital innovations in devices and circuits is now playing an important role. This paper analyzes the background of this change and defines new frontiers for device technology of sub-100 nm VLSIs.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133852069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A partially depleted 1.8 V SOI CMOS SRAM technology featuring a 3.77 /spl mu/m/sup 2/ cell 一种部分耗尽的1.8 V SOI CMOS SRAM技术，具有3.77 /spl mu/m/sup 2/ cell
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852813
K. Cox, J. Scott, S. Bishop, M. Bhat, B. Nettleton, D. Pan, M. Hamilton, D. Chang, L. Day, P. Schani
{"title":"A partially depleted 1.8 V SOI CMOS SRAM technology featuring a 3.77 /spl mu/m/sup 2/ cell","authors":"K. Cox, J. Scott, S. Bishop, M. Bhat, B. Nettleton, D. Pan, M. Hamilton, D. Chang, L. Day, P. Schani","doi":"10.1109/VLSIT.2000.852813","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852813","url":null,"abstract":"Summary form only given. A robust 1.8 V partially-depleted SOI SRAM technology has been developed from the 0.20 /spl mu/m bulk CMOS process platform with copper interconnect. The 3.77 /spl mu/m/sup 2/ 6T bitcell features self-aligned local interconnect (SALI) with buried channel PFET (BCPFET) load devices. The technology was used in fabrication of a dense 4 Mb asynchronous SOI SRAM originally designed for bulk Si but modified for SOI fabrication. SOI VLSI die yield equivalent to bulk Si was realized and excellent reliability results were achieved.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116331828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improvement of the tail component in retention time distribution using buffered n-implantation with tilt and rotation (BNITR) for 0.2 um DRAM cell and beyond 利用倾斜和旋转缓冲氮注入(BNITR)改善0.2 um及以上DRAM电池尾部组件的保留时间分布
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852780
I. Kim, N. Kim, H. Jung, H. Kwon, Seung-Han Ok, Jongmin Kim, P. Sim, Joosung Park, Dae-Young Park, S. Jang
{"title":"Improvement of the tail component in retention time distribution using buffered n-implantation with tilt and rotation (BNITR) for 0.2 um DRAM cell and beyond","authors":"I. Kim, N. Kim, H. Jung, H. Kwon, Seung-Han Ok, Jongmin Kim, P. Sim, Joosung Park, Dae-Young Park, S. Jang","doi":"10.1109/VLSIT.2000.852780","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852780","url":null,"abstract":"The novel junction process scheme in DRAM memory cell with 0.2 um design rule and STI (Shallow Trench Isolation) has been investigated to improve the tail component of DRAM retention time distribution. In this paper, we propose BNITR (Buffered N-Implantation with Tilt and Rotation) process scheme that is designed on the basis of the local field-enhancement model of the tail component and report an excellent improvement effect in tail distribution of retention time without device degradation.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129401925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel CVD polymeric anti-reflective coating (PARC) for DRAM, flash and logic device with 0.1 /spl mu/m CoSi/sub 2/ gate 一种新型的CVD聚合物抗反射涂层(PARC)，用于0.1 /spl mu/m CoSi/sub 2/栅极的DRAM、闪存和逻辑器件
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852764
K. Linliu, Mai-Rue Kuo, Yi-Ren Huang, Shu-Chun Lin, S. Jeng, Chunshing Chen
{"title":"A novel CVD polymeric anti-reflective coating (PARC) for DRAM, flash and logic device with 0.1 /spl mu/m CoSi/sub 2/ gate","authors":"K. Linliu, Mai-Rue Kuo, Yi-Ren Huang, Shu-Chun Lin, S. Jeng, Chunshing Chen","doi":"10.1109/VLSIT.2000.852764","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852764","url":null,"abstract":"A novel CVD polymeric anti-reflective coating (PARC) process has been developed for KrF lithography. The refractive index, n, and extinction coefficient, k, of PARC are tuned to match the optical properties of substrates. PARC is a conformal layer of thin polymer film, which significantly improves the CD uniformity of critical layers such as Poly Si gate and other features over topography. Since PARC is a pure polymeric material, it is easily removed by the conventional dry ash process. The ease of removal of PARC from Poly Si is particularly beneficial to the formation of salicide for advanced logic devices. In this paper, PARC is used to fabricate devices with 0.1 /spl mu/m CoSi/sub 2/ gate. Furthermore, the etching rate of PARC is about 500% higher than that of organic BARC for DUV photoresist, so that there is less DUV resist loss during ARC open step. PARC is a useful and low-cost process to extend KrF lithography for sub-0.15 /spl mu/m devices.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129929737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A modular 0.13 /spl mu/m bulk CMOS technology for high performance and low power applications 模块化0.13 /spl mu/m批量CMOS技术，适用于高性能和低功耗应用
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852749
L. K. Han, S. Biesemans, J. Heidenreich, K. Houlihan, C. Lin, V. McGahay, T. Schiml, A. Schmidt, U. Schroeder, M. Stetter, C. Wann, D. Warner, R. Mahnkopf, B. Chen
{"title":"A modular 0.13 /spl mu/m bulk CMOS technology for high performance and low power applications","authors":"L. K. Han, S. Biesemans, J. Heidenreich, K. Houlihan, C. Lin, V. McGahay, T. Schiml, A. Schmidt, U. Schroeder, M. Stetter, C. Wann, D. Warner, R. Mahnkopf, B. Chen","doi":"10.1109/VLSIT.2000.852749","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852749","url":null,"abstract":"A leading-edge 0.13 /spl mu/m generation CMOS technology is presented as a platform for systems on a chip (SOC) applications. A modular triple gate oxide process concept is introduced for the first time to allow the optimization of high performance devices, low leakage devices, and I/O devices independently. Process commonality is also achieved to support deep-trench based embedded DRAM. Seven levels of Cu interconnects integrated with low-k ILD have been developed. With mature KrF 248 nm lithography and optical enhancement techniques, aggressive design rules are achieved to meet the circuit density requirement. A 2.48 /spl mu/m/sup 2/ functional 6T-SRAM cell is demonstrated.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"14 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120930936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
An epitaxial channel MOSFET for improving flicker noise under low supply voltage 一种用于改善低电源电压下闪烁噪声的外延沟道MOSFET
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI: 10.1109/VLSIT.2000.852809
T. Ohguro, R. Hasumi, T. Ishikawa, M. Nishigori, H. Oyamatsu, F. Matsuoka
{"title":"An epitaxial channel MOSFET for improving flicker noise under low supply voltage","authors":"T. Ohguro, R. Hasumi, T. Ishikawa, M. Nishigori, H. Oyamatsu, F. Matsuoka","doi":"10.1109/VLSIT.2000.852809","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852809","url":null,"abstract":"We investigated the analog performance of a 0.11 /spl mu/m CMOS under a low supply voltage. In order to avoid flicker noise degradation under the low supply voltage, an epitaxial channel MOSFET without halo implantation was shown to be effective.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121690402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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