模块化0.13 /spl mu/m批量CMOS技术，适用于高性能和低功耗应用

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852749

L. K. Han, S. Biesemans, J. Heidenreich, K. Houlihan, C. Lin, V. McGahay, T. Schiml, A. Schmidt, U. Schroeder, M. Stetter, C. Wann, D. Warner, R. Mahnkopf, B. Chen

{"title":"模块化0.13 /spl mu/m批量CMOS技术，适用于高性能和低功耗应用","authors":"L. K. Han, S. Biesemans, J. Heidenreich, K. Houlihan, C. Lin, V. McGahay, T. Schiml, A. Schmidt, U. Schroeder, M. Stetter, C. Wann, D. Warner, R. Mahnkopf, B. Chen","doi":"10.1109/VLSIT.2000.852749","DOIUrl":null,"url":null,"abstract":"A leading-edge 0.13 /spl mu/m generation CMOS technology is presented as a platform for systems on a chip (SOC) applications. A modular triple gate oxide process concept is introduced for the first time to allow the optimization of high performance devices, low leakage devices, and I/O devices independently. Process commonality is also achieved to support deep-trench based embedded DRAM. Seven levels of Cu interconnects integrated with low-k ILD have been developed. With mature KrF 248 nm lithography and optical enhancement techniques, aggressive design rules are achieved to meet the circuit density requirement. A 2.48 /spl mu/m/sup 2/ functional 6T-SRAM cell is demonstrated.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"14 12","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":"{\"title\":\"A modular 0.13 /spl mu/m bulk CMOS technology for high performance and low power applications\",\"authors\":\"L. K. Han, S. Biesemans, J. Heidenreich, K. Houlihan, C. Lin, V. McGahay, T. Schiml, A. Schmidt, U. Schroeder, M. Stetter, C. Wann, D. Warner, R. Mahnkopf, B. Chen\",\"doi\":\"10.1109/VLSIT.2000.852749\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A leading-edge 0.13 /spl mu/m generation CMOS technology is presented as a platform for systems on a chip (SOC) applications. A modular triple gate oxide process concept is introduced for the first time to allow the optimization of high performance devices, low leakage devices, and I/O devices independently. Process commonality is also achieved to support deep-trench based embedded DRAM. Seven levels of Cu interconnects integrated with low-k ILD have been developed. With mature KrF 248 nm lithography and optical enhancement techniques, aggressive design rules are achieved to meet the circuit density requirement. A 2.48 /spl mu/m/sup 2/ functional 6T-SRAM cell is demonstrated.\",\"PeriodicalId\":268624,\"journal\":{\"name\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"volume\":\"14 12\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"24\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2000.852749\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2000.852749","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 24

摘要

领先的0.13 /spl mu/m一代CMOS技术作为片上系统(SOC)应用的平台。首次引入模块化三栅氧化工艺概念，可独立优化高性能器件、低泄漏器件和I/O器件。为了支持基于深沟槽的嵌入式DRAM，还实现了工艺通用性。开发了7级低钾ILD集成铜互连。利用成熟的KrF 248nm光刻技术和光学增强技术，实现了严格的设计规则，以满足电路密度要求。演示了2.48 /spl mu/m/sup 2/功能性6T-SRAM单元。

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A modular 0.13 /spl mu/m bulk CMOS technology for high performance and low power applications

A leading-edge 0.13 /spl mu/m generation CMOS technology is presented as a platform for systems on a chip (SOC) applications. A modular triple gate oxide process concept is introduced for the first time to allow the optimization of high performance devices, low leakage devices, and I/O devices independently. Process commonality is also achieved to support deep-trench based embedded DRAM. Seven levels of Cu interconnects integrated with low-k ILD have been developed. With mature KrF 248 nm lithography and optical enhancement techniques, aggressive design rules are achieved to meet the circuit density requirement. A 2.48 /spl mu/m/sup 2/ functional 6T-SRAM cell is demonstrated.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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