一种部分耗尽的1.8 V SOI CMOS SRAM技术，具有3.77 /spl mu/m/sup 2/ cell

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852813

K. Cox, J. Scott, S. Bishop, M. Bhat, B. Nettleton, D. Pan, M. Hamilton, D. Chang, L. Day, P. Schani

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引用次数: 1

摘要

只提供摘要形式。基于0.20 /spl mu/m的铜互连体CMOS工艺平台，开发了一种强大的1.8 V部分耗尽SOI SRAM技术。3.77 /spl mu/m/sup 2/ 6T位单元具有自对准本地互连(SALI)和埋道pet (BCPFET)负载器件。该技术用于制造高密度4mb异步SOI SRAM，最初设计用于块状Si，但修改用于SOI制造。实现了SOI VLSI芯片等效体积硅的良率，并取得了良好的可靠性结果。

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A partially depleted 1.8 V SOI CMOS SRAM technology featuring a 3.77 /spl mu/m/sup 2/ cell

Summary form only given. A robust 1.8 V partially-depleted SOI SRAM technology has been developed from the 0.20 /spl mu/m bulk CMOS process platform with copper interconnect. The 3.77 /spl mu/m/sup 2/ 6T bitcell features self-aligned local interconnect (SALI) with buried channel PFET (BCPFET) load devices. The technology was used in fabrication of a dense 4 Mb asynchronous SOI SRAM originally designed for bulk Si but modified for SOI fabrication. SOI VLSI die yield equivalent to bulk Si was realized and excellent reliability results were achieved.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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