高品质的La/sub 2/O/sub 3/和Al/sub 2/O/sub 3/栅极电介质，等效氧化厚度为5-10 /spl

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852751

A. Chin, Y.H. Wu, S.B. Chen, C. Liao, W. Chen

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引用次数: 64

摘要

制备了高质量的La/sub 2/O/sub 3/和Al/sub 2/O/sub 3/， EOT分别为4.8和9.6 /spl Aring/，漏电流分别为0.06和0.4 A/cm/sup -2/， D/sub /分别为3/spl倍/10/sup 10/ eV/sup -1//cm/sup 2/。高K进一步证明了高的MOSFET的I/sub d/和g/sub m/与低I/sub OFF/。获得了良好的SILC和Q/sub / BD/，可与SiO/sub / 2/相媲美。较低的EOT是由于与Si接触时具有较高的热力学稳定性，并且在高温/低温/退火后温度高达550/spl℃。

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High quality La/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/ gate dielectrics with equivalent oxide thickness 5-10 /spl Aring/

High quality La/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/ are fabricated with EOT of 4.8 and 9.6 /spl Aring/, leakage current of 0.06 and 0.4 A/cm/sup -2/ and D/sub it/ of both 3/spl times/10/sup 10/ eV/sup -1//cm/sup 2/, respectively. The high K is further evidenced from high MOSFET's I/sub d/ and g/sub m/ with low I/sub OFF/. Good SILC and Q/sub BD/ are obtained and comparable with SiO/sub 2/. The low EOT is due to the high thermodynamic stability in contact with Si and stable after H/sub 2/ annealing up to 550/spl deg/C.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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