N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi, T. Oashi, K. Tsukamoto, S. Komori, K. Tomita, T. Inbe, R. Ohsaki, T. Hanawa, S. Sakamori, M. Shirahata, J. Tsuchimoto, T. Eimori
{"title":"采用W/多晶硅栅极和Cu双金属化技术，实现了DRAM节距为0.38 /spl μ m, LOGIC节距为0.42 /spl μ m的高密度嵌入式DRAM技术","authors":"N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi, T. Oashi, K. Tsukamoto, S. Komori, K. Tomita, T. Inbe, R. Ohsaki, T. Hanawa, S. Sakamori, M. Shirahata, J. Tsuchimoto, T. Eimori","doi":"10.1109/VLSIT.2000.852770","DOIUrl":null,"url":null,"abstract":"A high density Embedded DRAM technology has been developed with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC/SRAM. This technology includes (1)W/WNx polymetal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-plugged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology realizes both very small. DRAM cell size of 0.29 /spl mu/m SRAM cell size of 2.77 /spl mu/m/sup 2/ on the same die.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"High density embedded DRAM technology with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization\",\"authors\":\"N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi, T. Oashi, K. Tsukamoto, S. Komori, K. Tomita, T. Inbe, R. Ohsaki, T. Hanawa, S. Sakamori, M. Shirahata, J. Tsuchimoto, T. Eimori\",\"doi\":\"10.1109/VLSIT.2000.852770\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high density Embedded DRAM technology has been developed with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC/SRAM. This technology includes (1)W/WNx polymetal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-plugged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology realizes both very small. DRAM cell size of 0.29 /spl mu/m SRAM cell size of 2.77 /spl mu/m/sup 2/ on the same die.\",\"PeriodicalId\":268624,\"journal\":{\"name\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"volume\":\"108 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2000.852770\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2000.852770","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High density embedded DRAM technology with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization
A high density Embedded DRAM technology has been developed with 0.38 /spl mu/m pitch in DRAM and 0.42 /spl mu/m pitch in LOGIC/SRAM. This technology includes (1)W/WNx polymetal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-plugged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology realizes both very small. DRAM cell size of 0.29 /spl mu/m SRAM cell size of 2.77 /spl mu/m/sup 2/ on the same die.
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