A 0.135 /spl mu/m/sup 2/ 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852777

C. Radens, U. Gruening, J. Mandelman, M. Seitz, D. Lea, D. Casarotto, L. Clevenger, L. Nesbit, R. Malik, S. Halle, S. Kudelka, H. Tews, R. Divakaruni, J. Sim, A. Strong, D. Tibbel, N. Arnold, S. Bukofsky, J. Preuninger, G. Kunkel, G. Bronner

引用次数: 2

Abstract

A 0.135 /spl mu/m/sup 2/ trench-capacitor DRAM cell with a trench-sidewall vertical-channel array device has been fabricated using 150 nm groundrules and optical lithography. This 6F/sup 2/ cell features a novel active area layout, a trench-top-oxide (TTO) isolation between trench capacitor and trench gate, maskless self-aligned buried strap node contact, shallow trench isolation (STI), a self-aligned poly-plug bit contact, and two levels of bitline interconnect, both formed using a W dual-damascene process.

查看原文本刊更多论文

一个0.135 /spl mu/m/sup 2/ 6F/sup 2/沟槽侧壁垂直器件单元，用于4gb / 16gb DRAM

采用150 nm基材和光刻技术，制备了一种0.135 /spl mu/m/sup 2/沟槽电容DRAM单元，该单元具有沟槽侧壁垂直通道阵列器件。这种6F/sup /电池具有新颖的有源区域布局、沟槽电容和沟槽栅极之间的沟槽顶氧化物(TTO)隔离、无掩模自定向埋带节点触点、浅沟槽隔离(STI)、自定向多插头位触点和两级位线互连，均采用W双damascene工艺形成。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

自引率

0.00%

发文量