A partially depleted 1.8 V SOI CMOS SRAM technology featuring a 3.77 /spl mu/m/sup 2/ cell

Abstract

Summary form only given. A robust 1.8 V partially-depleted SOI SRAM technology has been developed from the 0.20 /spl mu/m bulk CMOS process platform with copper interconnect. The 3.77 /spl mu/m/sup 2/ 6T bitcell features self-aligned local interconnect (SALI) with buried channel PFET (BCPFET) load devices. The technology was used in fabrication of a dense 4 Mb asynchronous SOI SRAM originally designed for bulk Si but modified for SOI fabrication. SOI VLSI die yield equivalent to bulk Si was realized and excellent reliability results were achieved.