用于0.16-/spl mu/m CMOS技术的简单嵌入式DRAM工艺

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852769

C. Liu, P.W. Diodato, S. Rogers, W. Lai, C. Chen, E. J. Lloyd, C.Y. Sun, D. Barr, R. Liu, C. Chang, L. Trimble, C. Pai, H. Vaidya

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摘要

提出了一种简单的嵌入式DRAM (eDRAM)工艺，可将前端附加成本降至最低，适用于0.16-/spl mu/m CMOS技术。该结构导致低泄漏器件(在100/spl度/C下<20 fA/cell)适合未来几代edram。在不使用多晶硅插头或金属-0位线走线的情况下，其形貌与核心LOGIC工艺相同。低温MIM电容器很容易集成使用金属-2级的w插头。总共额外的平版印刷步骤只有3-5个。

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A simple embedded DRAM process for 0.16-/spl mu/m CMOS technologies

A simple embedded DRAM (eDRAM) process that minimizes the front-end add-on cost is presented for 0.16-/spl mu/m CMOS technologies. The structure results in a low-leakage device (<20 fA/cell at 100/spl deg/C) suitable for future generations of eDRAMs. Without using poly-Si plugs or metal-0 bit-line runners, topography is identical to the core LOGIC process. Low-temperature MIM capacitors are easily integrated using the W-plugs of metal-2 level. The number of total additional lithographic steps is only 3-5.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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