0.13 /spl mu/m DRAM技术，适用于千兆比特密度的单机和嵌入式DRAM

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852748

K.N. Kim, T. Chung, H. Jeong, J. Moon, Y.W. Park, G. Jeong, K. Lee, G. Koh, D.W. Shin, Y. Hwang, D. Kwak, H. Uh, D. Ha, J. Lee, S. Shin, M. Lee, Y. Chun, J.K. Lee, B.J. Park, J. Oh, J.G. Lee, S. Lee

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引用次数: 8

摘要

本文采用KrF光刻技术开发了0.13 /spl mu/m的DRAM技术。为了将KrF光刻扩展到0.13 /spl mu/m一代，开发了全CMP技术，以提供平坦的表面。全自对准触点(SAC)技术可使存储单元着陆垫和存储节点触点插头以字线和位线自对准的方式形成，从而使存储单元加工变得容易。通过这些技术，可以很容易地实现极小的存储单元，而不会造成任何产量损失。Al/sub 2/O/sub 3/的低温PAOCS MIS电容器可以大大降低金属接触的纵横比，从而产生稳定的金属接触过程。它可以使DRAM技术更容易地与逻辑过程融合。在1gb DRAM上成功演示了0.13 /spl mu/m集成技术。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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