一种具有自对准沟槽晶体管和隔离结构的闪存EEPROM单元

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852795

K. Nakagawa, K. Yoshida, S. Masuda, A. Yoshino, I. Sakai

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引用次数: 0

摘要

针对未来高密度非接触式nor型闪存eeprom，提出了一种具有自对准沟槽晶体管和隔离结构的存储单元，并对其可行性进行了论证。当隧道氧化物厚度为9 nm时，短通道效应被明显抑制到特征尺寸(F)为0.14 /spl mu/m，并且实现了面积为0.16 /spl mu/m/sup 2/ (8F/sup 2/， F=0.14 /spl mu/m)的优异的持久性能(bbb10 /sup 5/ Fowler-Nordheim写/擦除周期)。

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A flash EEPROM cell with self-aligned trench transistor and isolation structure

For future high-density contactless-NOR-type flash EEPROMs, a new memory cell with self-aligned trench transistor and isolation structure has been proposed, and its feasibility was demonstrated. The short channel effect was suppressed markedly down to the feature size (F) of 0.14 /spl mu/m with the tunnel oxide thickness of 9 nm, and excellent endurance performance (>10/sup 5/ Fowler-Nordheim write/erase cycles) of the memory cell with the area of 0.16 /spl mu/m/sup 2/ (8F/sup 2/, F=0.14 /spl mu/m) was realized.

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来源期刊

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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