0.13 /spl mu/m一代SOC(片上系统)的CMOS技术平台

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852802

H. Yoshimura, T. Nakayama, M. Nishigohri, M. Inohara, K. Miyashita, E. Morifuji, A. Oishi, H. Kawashima, M. Habu, H. Koike, H. Takato, Y. Toyoshima, H. Ishiuchi

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引用次数: 3

摘要

在本文中，我们展示了0.13 /spl mu/m一代SOC(片上系统)的平台技术。介绍了采用沟槽电容DRAM单元为0.3 /spl mu/m/sup 2/和6Tr SRAM单元为2.5 /spl mu/m/sup 2/的0.11 /spl mu/m逻辑工艺。通过使用一次性栅极侧壁，在深结激活后形成源/漏扩展。因此，理想的退火条件适用于浅结形成的源/漏扩展。此外，优化了Co盐化剂的第二侧壁，以抑制p/sup +/多晶硅栅中硼的渗透。

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A CMOS technology platform for 0.13 /spl mu/m generation SOC (system on a chip)

In this paper, we demonstrate a platform technology for 0.13 /spl mu/m generation SOC (system on a chip). 0.11 /spl mu/m LOGIC process with trench capacitor DRAM cell of 0.3 /spl mu/m/sup 2/ and 6Tr SRAM cell of 2.5 /spl mu/m/sup 2/ is described. Source/drain extensions are formed after deep junction activation by using disposable gate sidewalls. Thus ideal annealing condition is applied to source/drain extensions for shallow junction formation. In addition, second sidewalls for Co salicide are optimized for suppression of boron penetration from p/sup +/ poly-silicon gate.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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