A 0.99-/spl mu/m/sup 2/ loadless four-transistor SRAM cell in 0.13-/spl mu/m generation CMOS technology

Abstract

Summary form only given. We present an ultra-high-density embedded loadless four-transistor SRAM cell for 0.13-/spl mu/m logic LSIs. The cell size is 0.99 /spl mu/m/sup 2/, which is the smallest of all reported SRAM cells. In addition, its fabrication process is fully compatible with CMOS logic technologies. The following three technologies reduce the cell area to less than 1 /spl mu/m/sup 2/, and provide highly stable operation at 1.2 V. The double-exposure technique using KrF excimer laser lithography with complementary phase-shift masks reduces the spacing between the drive-transistor gate and the word line. Using the borderless-contact etching process expands shared contact up to 0.21 /spl mu/m without contact leakage current to obtain sufficient misalignment tolerance. The thickness of the gate dielectrics in the cell is controlled to suppress the direct tunneling current to less than the off-state current in order to retain the cell data from -40 to 125/spl deg/C.