An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC)

Abstract

An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC) is presented using the models for global signal, clock, and power supply wiring networks. Based on the models for wiring resource demand, noise limit, and bandwidth requirement, an interconnect design plane is proposed. The new design plane demonstrates the limits imposed on global on-chip interconnect physical dimensions for future technology generations.