超薄SiO/ sub2 /在低电压下击穿测量

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) Pub Date : 2000-06-13 DOI:10.1109/VLSIT.2000.852783

J. Stathis, A. Vayshenker, P. Varekamp, E. Wu, C. Montrose, J. McKenna, D. DiMaria, L. Han, E. Cartier, R. Wachnik, B. Linder

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引用次数: 22

摘要

在V/sub g/=1.9-4V的电压范围内，氧化厚度从t/sub ox/=1.4到2.2nm的mosfet已经应力超过一年。将所得数据与以往的模型计算结果进行了比较。电荷击穿的电压加速(Q/sub BD/)可以解释为击穿时临界缺陷密度(N/sup BD/)的电压依赖性较弱，但在统计学上具有显著意义，而对于所研究的最薄的氧化物，缺陷产生概率(P/sub g/)的电压依赖性强于预期。

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Breakdown measurements of ultra-thin SiO/sub 2/ at low voltage

MOSFETs with oxide thickness from t/sub ox/=1.4 to 2.2nm have been stressed for times exceeding one year, at voltages in the range V/sub g/=1.9-4V. The data are compared with previous model calculations. The voltage acceleration of the charge-to-breakdown (Q/sub BD/) is explained in terms of a weak yet statistically significant voltage dependence of the critical defect density at breakdown (N/sup BD/), and a stronger than expected voltage dependence of the defect generation probability (P/sub g/) for the thinnest oxides studied.

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2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

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