Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS

Abstract

We propose a new process of selective lateral under-etching of bi-layered Si/SiGe gates, aimed at the formation of well-controlled notches. Weak Ge mole fraction (/spl les/30%) and moderate notch depth render the notch formation compatible with standard CMOS process, and prevent dispersions. The latter, in the case of a shallow notch (/spl les/25 nm) are even smaller than in reference Si-gate devices without a notch. Higher commutation speed, better transconductance and better SGE/DIBL immunity are demonstrated experimentally on notched gate devices.