Low temperature (<500/spl deg/C) SrTiO/sub 3/ capacitor process technology for embedded DRAM

Abstract

We have developed low temperature SrTiO/sub 3/ (ST) capacitor process for embedded DRAM. ST film deposited at 475/spl deg/C was crystallized without additional annealing. 0.53nm SiO/sub 2/ equivalent thickness (teq) ST capacitor with Ru electrodes was obtained. The leakage current of the concave structure capacitor was less than 1fA/cell at /spl plusmn/0.8V for 256K 3-dimensional (3D) capacitors fabricated by the low temperature ST process. ST capacitor process can satisfy demands on lower processing temperature and scalability to very thin dielectric layer with low leakage current.