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1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)最新文献

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An efficient synthesizer for generation of fast parallel multipliers 用于生成快速并行乘法器的高效合成器
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786001
Shen-Fu Hsiao, M.-R. Jiang
{"title":"An efficient synthesizer for generation of fast parallel multipliers","authors":"Shen-Fu Hsiao, M.-R. Jiang","doi":"10.1109/VTSA.1999.786001","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786001","url":null,"abstract":"An automatic generator is developed which can synthesize fixed-point multipliers of any bit accuracy with speed performance comparable to other recent full-custom designs. This synthesizer performs global optimization on the interconnection of compression elements to minimize the delay in the partial product summation tree.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127957864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high efficient multiplier for the RS decoder RS解码器的高效乘法器
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786014
J. Jeng, J. Kuo, T.K. Tnuong
{"title":"A high efficient multiplier for the RS decoder","authors":"J. Jeng, J. Kuo, T.K. Tnuong","doi":"10.1109/VTSA.1999.786014","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786014","url":null,"abstract":"The field element multiplication plays an important role in the VLSI implementation of an RS decoder. In this paper, a high efficient multiplier is derived, which removes all the redundant computations. The fast multiplier uses only 64 AND gates and 83 XOR gates, and the total gate delay is 6.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132898295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 100-kbps power-line modem for household applications 100 kbps的家用电力线调制解调器
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786029
Yi-fu Chen, T. Chiueh
{"title":"A 100-kbps power-line modem for household applications","authors":"Yi-fu Chen, T. Chiueh","doi":"10.1109/VTSA.1999.786029","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786029","url":null,"abstract":"Communication using power line as a medium provides a convenient and inexpensive way for data transmission and control signaling in households. In this paper we introduce a power-line channel model as well as architecture of a spread-spectrum baseband transceiver IC for a powerline modem. The modulation and spreading scheme used in the proposed transceiver is MBOK. This transceiver runs at the carrier frequency of 256 kHz and provides 100 kbps data rate. Simulation results verify the effectiveness of the proposed architecture in household data communication.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133326703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
2.5 /spl Omega///spl square/ W/TiN/poly stack gate technology for high density and embedded DRAM technology 2.5 /spl Omega///spl square/ W/TiN/poly堆叠栅极技术，用于高密度和嵌入式DRAM技术
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786046
Y. Hu, D. Anderson, A. Rotondaro, S. OBrien, W. Hsu, R. Kraft, P. Tiner, P. Nicollian, S. Aur
{"title":"2.5 /spl Omega///spl square/ W/TiN/poly stack gate technology for high density and embedded DRAM technology","authors":"Y. Hu, D. Anderson, A. Rotondaro, S. OBrien, W. Hsu, R. Kraft, P. Tiner, P. Nicollian, S. Aur","doi":"10.1109/VTSA.1999.786046","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786046","url":null,"abstract":"A W/TiN/Poly gate stack has been developed and extensively characterized, and it is applied to a 0.2 /spl mu/m CMOS transistor design for Gigabit and embedded DRAM technology. The gate sheet is less than 2.5 /spl Omega///spl square/ with a 600 /spl Aring//200 /spl Aring//900 /spl Aring/ W/TiN/Poly gate stack at 0.16 /spl mu/m line width. The effective oxide thickness is found to be 3 /spl Aring/ thicker than a comparable poly-only gate. The oxide hard breakdown field can exceed 12 MV/cm and CHC lifetime is greater than 10 years with the W/TiN/Poly gate stack technology. In addition, a drive current of 400 /spl mu/A//spl mu/m for nMOS and 190 /spl mu/A//spl mu/m for pMOS have been achieved at 1 pA//spl mu/m off-current and 1.8 V Vcc with 5 nm gate oxide. This is the highest drive current reported to date for similar technologies.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130524926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling the impact of back-end process variation on circuit performance 模拟后端工艺变化对电路性能的影响
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.785999
D. Sylvester, O. S. Nakagawa, C. Hu
{"title":"Modeling the impact of back-end process variation on circuit performance","authors":"D. Sylvester, O. S. Nakagawa, C. Hu","doi":"10.1109/VTSA.1999.785999","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785999","url":null,"abstract":"We present a stochastic approach to account for on-chip interconnect process variation. A Monte Carlo approach is taken using actual process distributions to generate realistic 3-D performance corners. Accurate analytical models are used to provide a >3 order of magnitude speedup over simulation techniques. Resulting delay and noise performance spreads are 33 to 63% tighter than those found using a conventional technique. We apply this method to a clock distribution network to more precisely determine clock skew.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122225123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Novel Bi-directional tunneling program/erase NOR (BiNOR) type flash EEPROM 新型双向隧道编程/擦除NOR (BiNOR)型闪存EEPROM
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786036
E. Yang, Cheng-Jye Liu, T. Chao, M. Liaw, C. Hsu
{"title":"Novel Bi-directional tunneling program/erase NOR (BiNOR) type flash EEPROM","authors":"E. Yang, Cheng-Jye Liu, T. Chao, M. Liaw, C. Hsu","doi":"10.1109/VTSA.1999.786036","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786036","url":null,"abstract":"This paper presents a novel Bi-directional channel FN tunneling program/erase NOR (BiNOR) type flash memory cell for the reliable, high speed, and low power operation. With the localized shallow p-well at bit-line, BiNOR realizes low power channel FN tunneling program/erase in a NOR-type array architecture, which could only be done previously in a NAND array architecture. Furthermore, the read current is enhanced greatly by the 3-D conduction effect due to the designated shallow p-well.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127539416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved method for lateral profiling of interface traps and oxide charge in MOSFET devices MOSFET器件中界面阱和氧化物电荷横向轮廓的改进方法
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786007
A. Melik-Martirosian, T. Ma
{"title":"Improved method for lateral profiling of interface traps and oxide charge in MOSFET devices","authors":"A. Melik-Martirosian, T. Ma","doi":"10.1109/VTSA.1999.786007","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786007","url":null,"abstract":"An improved oxide-charge and interface-trap lateral profiling charge pumping technique is proposed. Erase-induced oxide charge and interface traps are investigated in Flash EPROM devices. It is shown that the improved technique allows the extraction of profiles in cases where the previous method does not yield satisfactory results.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Enhanced hot-hole degradation in P/sup +/-poly PMOSFETs with oxynitride gate dielectrics 氮化氧栅介质增强P/sup +/-聚pmosfet的热孔降解
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786006
Y. Chen, M. Gardner, J. Fulford, D. Wristers, A. Joshi, L. Chung, D. Kwong
{"title":"Enhanced hot-hole degradation in P/sup +/-poly PMOSFETs with oxynitride gate dielectrics","authors":"Y. Chen, M. Gardner, J. Fulford, D. Wristers, A. Joshi, L. Chung, D. Kwong","doi":"10.1109/VTSA.1999.786006","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786006","url":null,"abstract":"A significant degradation under hot-hole injection is observed in P/sup +/-poly PMOSFETs with oxynitride gate dielectrics. Both oxynitrides formed by gate oxide grown on Nitrogen Implanted Si Substrates (NISS) and NO-annealed SiO/sub 2/ oxynitride gate dielectrics are used and compared to control SiO/sub 2/ gate dielectrics of identical thicknesses. A physical model responsible for such enhanced degradation in PMOSFETs with oxynitride gate dielectric is proposed. It is shown that the hole injection barrier lowering as a result of the nitrogen-rich layer at the SiO/sub 2//Si interface in oxynitride is responsible for such enhanced degradation.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"155-156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114383549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Physical modeling of transient enhanced diffusion in silicon 硅中瞬态增强扩散的物理模拟
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.785990
K. Taniguchi, T. Saito, J. Xia, R. Kim
{"title":"Physical modeling of transient enhanced diffusion in silicon","authors":"K. Taniguchi, T. Saito, J. Xia, R. Kim","doi":"10.1109/VTSA.1999.785990","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785990","url":null,"abstract":"Transient enhanced diffusion (TED) of boron atoms in superlattice Si wafers during thermal annealing were simulated using a comprehensive diffusion model. It was found that the model well predicts boron atoms segregate to (311) defects during thermal annealing and normal TED as well.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116858172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new programming technique for flash memory devices 一种新的闪存设备编程技术
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786033
Z. Liu, Tengyu Ma
{"title":"A new programming technique for flash memory devices","authors":"Z. Liu, Tengyu Ma","doi":"10.1109/VTSA.1999.786033","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786033","url":null,"abstract":"A new programming scheme for flash memory devices, designated pulse agitated substrate hot electron injection (PASHEI), is demonstrated, which can be readily implemented with current cell structures without modification. Detailed comparison between CHEI and PASHEI is reported. Using this technique, excellent endurance characteristics are obtained up to 100 k cycles.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"95 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129134537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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