A high efficient multiplier for the RS decoder

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI:10.1109/VTSA.1999.786014

J. Jeng, J. Kuo, T.K. Tnuong

引用次数: 3

Abstract

The field element multiplication plays an important role in the VLSI implementation of an RS decoder. In this paper, a high efficient multiplier is derived, which removes all the redundant computations. The fast multiplier uses only 64 AND gates and 83 XOR gates, and the total gate delay is 6.

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RS解码器的高效乘法器

场元乘法在RS译码器的VLSI实现中起着重要的作用。本文推导了一种高效的乘法器，消除了所有的冗余计算。快速乘法器仅使用64个与门和83个异或门，总门延迟为6。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

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