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1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)最新文献

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IRAM: a microprocessor for the post-PC era IRAM:后pc时代的微处理器
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-10 DOI: 10.1109/VTSA.1999.785994
D. Patterson
{"title":"IRAM: a microprocessor for the post-PC era","authors":"D. Patterson","doi":"10.1109/VTSA.1999.785994","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785994","url":null,"abstract":"We call the technology we are using to build our version of the next generation of computers (personal mobile multimedia devices) Intelligent RAM, or IRAM. By building a processor inside a DRAM, we are continuing the progression of system integration dictated by Moore's Law, as a single chip now includes the processor and its memory. The first benefit is reducing size and power of the computer, as IRAM takes less space and power than multiple chips. At the same time, we get tremendous memory performance without relying on cache memory, thereby being a better match to the streaming, multimedia applications of tomorrow. We also integrate the network to increase its efficiency. With more system components integrated onto a single chip, system-wide error checking, diagnostics, and monitoring of entire information appliances becomes feasible.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126419722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-performancf ALPHA microprocessor design 高性能ALPHA微处理器设计
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-10 DOI: 10.1109/VTSA.1999.786009
D. Bailey
{"title":"High-performancf ALPHA microprocessor design","authors":"D. Bailey","doi":"10.1109/VTSA.1999.786009","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786009","url":null,"abstract":"Elements of successful high-performance microprocessor design are discussed. Subjects presented include clock distribution, latches, and design methods and techniques. General design trends are mentioned where appropriate. Tradeoffs between circuit performance and electrical integrity are emphasized throughout.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127045316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
MEMS technology and applications MEMS技术及应用
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-10 DOI: 10.1109/VTSA.1999.785985
D. Polla
{"title":"MEMS technology and applications","authors":"D. Polla","doi":"10.1109/VTSA.1999.785985","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785985","url":null,"abstract":"Summary form only given. This talk will primarily discuss several representative systems applications of microelectromechanical systems (MEMS) for smart physical sensing, minimally invasive surgery, robotics, and bioanalytic medicine. This talk will describe MEMS materials, processing technologies, and device applications including i) physical microsensors for detecting force, pressure, and acoustic energy, 2) microvalves, micropumps, and capillaries for microfluidic controls; 3) biosensors based on molecular recognition structures; 4) miniature linear micromotors for precision positioning and manipulation of cells; and 5) surgical and scientific microinstruments. Selected successful systems demonstration applications from the fields of ophthalmology, arthroscopic surgery, gynecology, and laboratory medicine will be presented. Design issues, technology limitations, systems integration approaches, and future opportunities of MEMS will be discussed.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134623804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A new self-convergent programming and erase tightening by substrate-hot-electron injection for ETOX cells in triple-well 三孔ETOX细胞基板热电子注入自收敛编程和擦除收紧新方法
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786034
M. Chi, Chih-Ming Chen, C. Hung, Yu-Hsiung Wang
{"title":"A new self-convergent programming and erase tightening by substrate-hot-electron injection for ETOX cells in triple-well","authors":"M. Chi, Chih-Ming Chen, C. Hung, Yu-Hsiung Wang","doi":"10.1109/VTSA.1999.786034","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786034","url":null,"abstract":"A new self-convergent programming technique for ETOX cells fabricated in a triple-well process is proposed using substrate hot-electron (SHE) injection. The programming efficiency is at least 100X higher than channel-hot-electron (CHE) injection. The cell threshold voltage (V/sub t/) after programming saturates with self-convergence. The SHE re-programming can tighten the Vt spread after erase. The NOR array architecture is codified with individual p-wells for each column so that it is possible to implement single-bit program and erase operations. The ETOX cells in triple-well with the new NOR array can perform as a full EEPROM as well as a flash memory.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125424777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Modeling and correlation of gate oxide Q/sub BD/ between exponential current ramp and constant current stresses 栅极氧化物Q/sub / BD/在指数电流斜坡和恒流应力之间的建模和关联
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786008
C.H. Liu, T. Cheng, Mu-Chun Wang, S.H. Yang, K. Fu
{"title":"Modeling and correlation of gate oxide Q/sub BD/ between exponential current ramp and constant current stresses","authors":"C.H. Liu, T. Cheng, Mu-Chun Wang, S.H. Yang, K. Fu","doi":"10.1109/VTSA.1999.786008","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786008","url":null,"abstract":"A simple model and conversion scheme is proposed to correlate Q/sub BD/ measured through exponential current ramp stress (ECR) and constant current stress (CCS). Although Q/sub BD/ measured via ECR depends on holding time (a power-law dependence) and so does CCS on current density (also a power-law dependence), results from either test at any stress condition can be easily converted to the other with stress condition specified. Experiments with 35 /spl Aring/ to 135 /spl Aring/ oxides demonstrate the capability of the proposed method.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115072597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Trends in digital signal processors 数字信号处理器的发展趋势
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786012
S.A. Mujtaba
{"title":"Trends in digital signal processors","authors":"S.A. Mujtaba","doi":"10.1109/VTSA.1999.786012","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786012","url":null,"abstract":"To facility the implementation of complex signal processing algorithms future DSPs will be required to deliver higher performance and ease of programmability without compromising power dissipation and code density. To meet these conflicting requirements, several architectures have been proposed such as EPIC, VLIW, and superscalar. In this paper, we chart the evolution of DSPs-starting from a simple Multiply-Accumulate engine and progressing to a system-on-a-chip embodying some variant of a parallel processing machine.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"419 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115078070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Embedded DRAM technology: past, present and future 嵌入式DRAM技术:过去、现在和未来
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786044
H. Takato, H. Koike, T. Yoshida, H. Ishiuchi
{"title":"Embedded DRAM technology: past, present and future","authors":"H. Takato, H. Koike, T. Yoshida, H. Ishiuchi","doi":"10.1109/VTSA.1999.786044","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786044","url":null,"abstract":"Issues and development trends with regard to embedded DRAM are reviewed with real implementations for 0.5 /spl mu/m, 0.35 /spl mu/m and 0.25 /spl mu/m generations. Future directions of the embedded DRAM technologies, including MOSFET structure, memory cells, process cost and performance, are also discussed.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128718206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fully integrated embedded DRAM technologies with high performance logic and commodity DRAM cells for system-on-a-chip 完全集成的嵌入式DRAM技术，具有高性能逻辑和用于片上系统的商品DRAM单元
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786045
H. Koike, H. Takato, K. Hiyama, S. Yoshida, H. Harakawa, K. Kokubun, T. Shimabukuro, S. Kato, M. Tamaoki, H. Okano, H. Sato, Y. Morimasa, T. Yamamoto, M. Tanaka, J. Kumagai, O. Yakabe, H. Naruse, H. Kamijo, K. Tomioka, H. Ishiuchi
{"title":"Fully integrated embedded DRAM technologies with high performance logic and commodity DRAM cells for system-on-a-chip","authors":"H. Koike, H. Takato, K. Hiyama, S. Yoshida, H. Harakawa, K. Kokubun, T. Shimabukuro, S. Kato, M. Tamaoki, H. Okano, H. Sato, Y. Morimasa, T. Yamamoto, M. Tanaka, J. Kumagai, O. Yakabe, H. Naruse, H. Kamijo, K. Tomioka, H. Ishiuchi","doi":"10.1109/VTSA.1999.786045","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786045","url":null,"abstract":"This paper demonstrates a process integration for high performance and small footprint embedded DRAMs. A trench capacitor cell and a self-aligned bit line contact are selected to maintain exactly the same size as commodity DRAM cells. The cell array region is covered with a thin SiN barrier against salicidation. Ti-salicide source/drain is used in the logic region. No retention time degradation and good circuit performance are confirmed.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114240473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Gigabit Ethernet over unshielded twisted pair cables 千兆以太网通过非屏蔽双绞线电缆
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786026
K. Azadet
{"title":"Gigabit Ethernet over unshielded twisted pair cables","authors":"K. Azadet","doi":"10.1109/VTSA.1999.786026","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786026","url":null,"abstract":"This paper presents 1000BASE-T, the physical layer of Gigabit Ethernet over copper. After an introduction to the overall Gigabit Ethernet standard, we describe unshielded twisted pair (UTP) channel impairments, modulation and coding of 1000BASE-T, the clocking scheme and start-up protocol. Finally, we summarize challenges in the monolithic VLSI implementation of a 1000BASE-T transceiver.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"GE-21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126564188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A fast-acquisition demodulation scheme for 2.4 GHz wireless DSSS transceiver VLSI 2.4 GHz无线DSSS收发器VLSI的快速采集解调方案
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786041
Hua-Chin Lee, Ching-Kae Tzou, Chorng-Kuang Wang, V. Dan
{"title":"A fast-acquisition demodulation scheme for 2.4 GHz wireless DSSS transceiver VLSI","authors":"Hua-Chin Lee, Ching-Kae Tzou, Chorng-Kuang Wang, V. Dan","doi":"10.1109/VTSA.1999.786041","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786041","url":null,"abstract":"In this paper, a CMOS cell based system VLSI design for Direct-Sequence Spread-Spectrum (DSSS) wireless LAN transceiver is presented. In addition, an efficient and fast-acquisition demodulation scheme is proposed to use in the receiver architecture. Implementation and testing results are also given. The proposed demodulation scheme can help to positively combine the received signal energy of multipaths so that the detection performance is improved by 3 dB in a typical frequency-selective indoor wireless communication environment. The proposed architecture can synchronize the PN code in 30 /spl mu/s and the chip size is 5600/spl times/4600 /spl mu/m/sup 2/. It can be operated from 3.3 V to 5 V and the power consumption ranges from 189 mW to 250 mW respectively.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124170230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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