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1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)最新文献

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Multiplexer based adder for media signal processing 基于多路复用器的媒体信号处理加法器
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786010
A. Farooqui, V. Oklobdzija, F. Chechrazi
{"title":"Multiplexer based adder for media signal processing","authors":"A. Farooqui, V. Oklobdzija, F. Chechrazi","doi":"10.1109/VTSA.1999.786010","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786010","url":null,"abstract":"This paper presents the design of a highly re-configurable adder, which has been optimized for speed and area. Since pass transistor based multiplexer is the fastest element in standard CMOS logic, we designed the adder using only multiplexers and 2-input inverted logic gates. This adder is the hybrid of binary carry lookahead adder of Brent, and carry select adder. By using the hybrid approach, the area and wiring of the adder is reduced by 1/2, keeping the adder delay proportional to O(log n). The critical path of the 68-bit partitioned adder consists of 7 two-to-one multiplexers and 1 XOR gate. The adder can be partitioned to support a variety of data formats, it can add two 64-bit-operands, four 32-bit operands, eight 16-bit operands, or sixteen and bit operands. The adder can be used for multi-media applications, and is well suited for VLIW processors. The adder is described in Verilog, and synthesized using Synopsys tool. The critical path delay of the 64-bit adder is 0.9 ns at typical conditions in standard cell 0.25 um technology.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122016435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Design and simulation of addressable failure site test structure for IC process control monitor 集成电路过程控制监视器可寻址故障现场测试结构的设计与仿真
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786039
K. Doong, J.Y. Cheng, Chen-Hsiang Hsu
{"title":"Design and simulation of addressable failure site test structure for IC process control monitor","authors":"K. Doong, J.Y. Cheng, Chen-Hsiang Hsu","doi":"10.1109/VTSA.1999.786039","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786039","url":null,"abstract":"A novel test structure to ensure failure addressable and high-density test structure of semiconductor process control monitor with a limited number of contact pads required for electrical test is described. The placement and routing scheme requires only two levels of conductive layers, and provides the maximum number of bridging and continuity test structure units. A graph model is developed to manifest the spatial configuration of test structure units and simplify the complexity of fault detection. Also, a generic algorithm of multi-fault detection was developed.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"144 27","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114052542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An efficient algorithm for the multiple constant multiplication problem 多常数乘法问题的一种高效算法
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786015
M. Chen, Jing-Yang Jou, Hen-Ming Lin
{"title":"An efficient algorithm for the multiple constant multiplication problem","authors":"M. Chen, Jing-Yang Jou, Hen-Ming Lin","doi":"10.1109/VTSA.1999.786015","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786015","url":null,"abstract":"In this paper, we propose an efficient solution for the problem of multiple constant multiplication (MCM). We first propose a spring algorithm to search the common subexpressions not only across the columns of the digit matrix but also across the rows to reduce the number of additions and subtractions. Moreover, an elasticizing algorithm, which exploits the negation and scaling techniques, is proposed to improve the impact of the spring algorithm further. The experimental results are very promising.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114583566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Channel formation for 0.15 /spl mu/m CMOS using through-the-gate implantation 0.15 /spl mu/m CMOS的通道形成采用通栅植入
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.785987
A. Montree, Y. Ponomarev, W. Baks, A. van Brandenburg, C. Dachs, S.F.M. Roes, J. Schmitz, P. Stolk, H. Tuinhout
{"title":"Channel formation for 0.15 /spl mu/m CMOS using through-the-gate implantation","authors":"A. Montree, Y. Ponomarev, W. Baks, A. van Brandenburg, C. Dachs, S.F.M. Roes, J. Schmitz, P. Stolk, H. Tuinhout","doi":"10.1109/VTSA.1999.785987","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785987","url":null,"abstract":"Front-end optimization of a 0.15 /spl mu/m CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 /spl mu/m CMOS transistor and circuit performance was obtained.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121738289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A micropower current-mode CMOS function approximation circuit 一种微功率电流型CMOS函数近似电路
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786057
N. Manaresi, R. Rovatti, E. Franchi, G. Baccarani
{"title":"A micropower current-mode CMOS function approximation circuit","authors":"N. Manaresi, R. Rovatti, E. Franchi, G. Baccarani","doi":"10.1109/VTSA.1999.786057","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786057","url":null,"abstract":"A current-mode weak-inversion circuit for analog function approximation is proposed. It is based on the fuzzy logic paradigm and exploits a modular architecture with respect to the number of inputs and the number of rules. Simulation results show that a 2-input, 1 output transcendental function can be approximated with a 50% RMS error at the expense of 5 /spl mu/W of power consumption with a 3.3 V supply.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124007027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel approach for the two-dimensional simulation of submicron MOSFETs using monotone iterative method 采用单调迭代法对亚微米mosfet进行二维模拟
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.785991
Yiming Li, S. Chung, Jinn-Liang Liu
{"title":"A novel approach for the two-dimensional simulation of submicron MOSFETs using monotone iterative method","authors":"Yiming Li, S. Chung, Jinn-Liang Liu","doi":"10.1109/VTSA.1999.785991","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785991","url":null,"abstract":"A new approach, called monotone iterative (MI) method, for the numerical solution of semiconductor device equations is presented. This constructive method is intended to alleviate some major difficulties particularly associated with Newton's method that is the principal methodology to date for the solution of nonlinear semiconductor device equations. The method converges globally with arbitrary initial guess under various bias conditions for a submicron MOSFET. By comparing with a Newton's iterative (NI) method, a speed-up factor of 30 in CPU time can be achieved by the MI method. The method is highly parallel and easy to implement for two- and three-dimensional simulations. Numerical simulations on a submicron N-MOSFET device with various biasing conditions and initial guesses are presented to demonstrate the efficiency of the method.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129510961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Extreme ultraviolet lithography for 0.1 /spl mu/m devices 用于0.1 /spl mu/m器件的极紫外光刻
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786017
S. Vaidya, D. Sweeney, R. Stulen, D. Attwood
{"title":"Extreme ultraviolet lithography for 0.1 /spl mu/m devices","authors":"S. Vaidya, D. Sweeney, R. Stulen, D. Attwood","doi":"10.1109/VTSA.1999.786017","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786017","url":null,"abstract":"Extreme Ultraviolet Lithography (EUVL) has emerged as one of the leading successors to optics for 0.1 /spl mu/m IC fabrication. Its strongest attribute is the potential to scale to much finer resolution at high throughput. As such, this technique could meet the lithography needs for Si ULSI down to fundamental device limits. In the United States, Lawrence Livermore, Sandia, and Lawrence Berkeley Laboratories are participating in an industry funded research effort to evolve EUV technology and build a prototype camera for lithographic exposure. More recently, both Europe and Japan have initiated government/industry sponsored programs in EUVL development. This talk focuses on program successes to date, and highlights some of the challenges that still lie ahead.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128234417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An embedded march algorithm test pattern generator for memory testing 用于内存测试的嵌入式行军算法测试模式生成器
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786037
Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang
{"title":"An embedded march algorithm test pattern generator for memory testing","authors":"Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang","doi":"10.1109/VTSA.1999.786037","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786037","url":null,"abstract":"The memory cores are essential for a system-on-a-chip (SOC). To test the memory cores, in this paper we propose a generalized embedded test pattern generator for any march algorithm. Without loss of functionality of the march algorithm, we also present a systematic procedure with a short time complexity to reduce the hardware cost of the test pattern generator.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129078145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An arbitrarily fast block processing architecture for decision feedback equalizers 决策反馈均衡器的任意快速块处理架构
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786028
Meng-Lin Yu, K. Azadet
{"title":"An arbitrarily fast block processing architecture for decision feedback equalizers","authors":"Meng-Lin Yu, K. Azadet","doi":"10.1109/VTSA.1999.786028","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786028","url":null,"abstract":"In this paper, a novel architecture is proposed to solve the decision feedback equalizer (DFE) critical path problem by parallel processing. This architecture uses the block processing technique. A block processing DFE with block factor of N takes N inputs and produces N outputs in parallel. Since each output computation depends on previous decisions, the computation of the N outputs forms a dependency chain in block processing DFEs and requires N-1 multiplexing delay time when it is done sequentially. Our architecture employs a fast, O(logN) multiplexing delay algorithm to resolve the output dependency and thus speeds up parallel block processing DFEs. Further, our architecture can be used with pipelining to completely eliminate the critical path problem. This architecture enables digital DFEs to be used in many important applications, such as very high speed data communication systems.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132744579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An enhanced model for planar inductors in CMOS technology CMOS技术中平面电感器的增强模型
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786021
Wen-Chi Wu, Y. Chan, Chorng-Kuang Wang
{"title":"An enhanced model for planar inductors in CMOS technology","authors":"Wen-Chi Wu, Y. Chan, Chorng-Kuang Wang","doi":"10.1109/VTSA.1999.786021","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786021","url":null,"abstract":"This paper presents an improved approach to model various spiral structures, which are widely employed in silicon technology. A turn-oriented model with closed form estimations is employed to depict the characteristics of spirals in the low GHz frequency band. Generalized formulas that eliminate complex 3-D electromagnetic analysis are derived for such passive components. The compact model, which is directly simplified from the enhanced model, provides a tradeoff between self-resonant frequency and quality factor under the standard CMOS technology.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114070818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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