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1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)最新文献

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The conversion of bulk CMOS circuits to SOI technology and its noise impact 块体CMOS电路转换为SOI技术及其噪声影响
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786055
Li-Kong Wang, H.H. Chen
{"title":"The conversion of bulk CMOS circuits to SOI technology and its noise impact","authors":"Li-Kong Wang, H.H. Chen","doi":"10.1109/VTSA.1999.786055","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786055","url":null,"abstract":"The faster switching speed and smaller parasitic capacitance of SOI circuits have provided 20% performance improvement over their bulk predecessors, but the characteristics of SOI circuits also introduced significant noise problems that cannot be overlooked. This paper addresses the design issues of remapping bulk CMOS circuits to the SOI technology, and discusses how to minimize the power supply noise by optimizing the placement of on-chip decoupling capacitors.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"43 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113965123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High-speed VLSI implementation of reduced complexity sequence estimation algorithms with application to Gigabit Ethernet 1000Base-T 高速VLSI实现的低复杂度序列估计算法及其在千兆以太网1000Base-T中的应用
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786027
E. Haratsch
{"title":"High-speed VLSI implementation of reduced complexity sequence estimation algorithms with application to Gigabit Ethernet 1000Base-T","authors":"E. Haratsch","doi":"10.1109/VTSA.1999.786027","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786027","url":null,"abstract":"This paper compares reduced complexity sequence estimation (RCSE) algorithms in terms of SNR performance, VLSI implementation, hardware complexity and critical path. A novel architecture is presented which reduces the hardware complexity of RCSE and relaxes the critical path problem. This architecture can be used to implement RCSE for Gigabit Ethernet 1000Base-T.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129128477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Spectroscopic Anisotropy Micro-Ellipsometry (SAME) for determination of lateral and vertical dimensions of sub-micron lithographic structures 光谱各向异性微椭圆偏振法测定亚微米光刻结构的横向和纵向尺寸
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786018
A. Michaelis, O. Gent, U. Mantz
{"title":"Spectroscopic Anisotropy Micro-Ellipsometry (SAME) for determination of lateral and vertical dimensions of sub-micron lithographic structures","authors":"A. Michaelis, O. Gent, U. Mantz","doi":"10.1109/VTSA.1999.786018","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786018","url":null,"abstract":"A new metrology tool, Spectroscopic Anisotropy Micro-Ellipsometry (SAME) is introduced. The method allows for a rapid and precise measurement of lateral and vertical feature sizes of periodic structures showing form birefringence. Examples of CD (critical dimensions), taper angle as well as overlay rotation measurements for gigabit generation DRAM structures are presented.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127193296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Array pass transistor design in trench cell for Gbit DRAM and beyond gb DRAM及以后的沟槽单元阵列通管设计
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786047
Y. Li, J. Mandelman, P. Parries, Y. Matsubara, Q. Ye, R. Rengarajan, J. Alsmeier, B. Flietner, D. Wheeler, H. Akatsu, R. Divakaruni, R. Mohler, K. Sunouchi, G. Bronner, T. Chen
{"title":"Array pass transistor design in trench cell for Gbit DRAM and beyond","authors":"Y. Li, J. Mandelman, P. Parries, Y. Matsubara, Q. Ye, R. Rengarajan, J. Alsmeier, B. Flietner, D. Wheeler, H. Akatsu, R. Divakaruni, R. Mohler, K. Sunouchi, G. Bronner, T. Chen","doi":"10.1109/VTSA.1999.786047","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786047","url":null,"abstract":"Aggressive scaling of the DRAM cell size requires minimum dimensions in both the channel length and the channel width of the array pass transistor. As a result of the stringent leakage current requirement, the design for the array MOSFET becomes increasingly challenging as cell size is reduced. In this paper, we present data that illustrate the importance of the channel and the source/drain engineering, along with considerations of minimizing the junction leakage. By utilizing a 512 k array diagnostic monitor, a methodology is presented for optimum array cell design in a statistically reliable manner. Design issues unique to the trench capacitor cell are covered. Alternative biasing schemes that boost the process window are also discussed.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133457258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An interconnect-centric design flow for nanometer technologies 以互联为中心的纳米技术设计流程
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.785998
J. Cong
{"title":"An interconnect-centric design flow for nanometer technologies","authors":"J. Cong","doi":"10.1109/VTSA.1999.785998","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785998","url":null,"abstract":"As integrated circuits (ICs) are scaled into nanometer dimensions and operate in giga-hertz frequencies, interconnect design and optimization have become critical in determining system performance and reliability. This paper presents the ongoing research effort at UCLA to develop an interconnect-centric design flow, including interconnect planning, interconnect synthesis, and interconnect layout, which allows interconnect design and optimization to be properly considered at every level of the design process. Efficient interconnect performance estimation models and tools at various levels are also being developed to support such an interconnect-centric design flow.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132788467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 199
Practical resolution limit of KrF lithography KrF光刻的实际分辨率极限
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786016
R. Schuster
{"title":"Practical resolution limit of KrF lithography","authors":"R. Schuster","doi":"10.1109/VTSA.1999.786016","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786016","url":null,"abstract":"Since lithography represents a major part of chip manufacturing costs it is desirable to extend KrF optical lithography to 0.15 /spl mu/m design rules and beyond. This paper discusses the resolution limits that can be achieved with state-of-the-art 0.68 NA exposure systems and optical enhancement techniques such as modified illumination, phase shift masks and optical proximity corrections. The goal is to optimize the imaging process to achieve process windows large enough for use in a manufacturing environment.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129487222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design challenges for high-performance SOI digital CMOS VLSI 高性能SOI数字CMOS VLSI的设计挑战
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786052
C. Chuang
{"title":"Design challenges for high-performance SOI digital CMOS VLSI","authors":"C. Chuang","doi":"10.1109/VTSA.1999.786052","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786052","url":null,"abstract":"This paper reviews the recent advances of SOI for high-performance digital CMOS VLSI applications. The technology/device requirements and design issues/challenges for high-performance, general-purpose microprocessor applications are differentiated with respect to low-power portable applications. Particular emphasis is placed on the impact of floating-body in partially-depleted devices on the circuit operation, stability, and functionality. Unique SOI design aspects such as the parasitic bipolar effect and hysteretic V/sub T/ variation are addressed. Circuit techniques to improve the noise immunity and global design issues are discussed.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122965433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analog front-end macro circuit design 模拟前端宏电路设计
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786040
B. Song
{"title":"Analog front-end macro circuit design","authors":"B. Song","doi":"10.1109/VTSA.1999.786040","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786040","url":null,"abstract":"Analog front-end electronics for wireless and digital communications systems encompass a broad range of functions such as LNA, down-mixer, IF amp, up-mixer, TX amp, AGC, filters and ADC/DAC, etc. Depending on system configurations and requirements, performance and design criteria also vary. This work aims to give an insight into critical analog design issues from the system perspectives. Topics to be discussed are RF isolation issues in integrating a whole system on a CMOS single die, an ADC architecture for software radio, and a low-voltage ADC technique for 1V single battery operation.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131040314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High quality ultra-thin (2.4 nm) oxide prepared by clustered vertical furnace with in-situ HF-vapor pre-gate oxide cleaning 采用簇式竖炉原位hf -蒸汽预栅氧化清洗法制备高品质超薄(2.4 nm)氧化物
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786003
T. Chao, J.L. Chen, C.S. Lai, H. Lin, T. Huang
{"title":"High quality ultra-thin (2.4 nm) oxide prepared by clustered vertical furnace with in-situ HF-vapor pre-gate oxide cleaning","authors":"T. Chao, J.L. Chen, C.S. Lai, H. Lin, T. Huang","doi":"10.1109/VTSA.1999.786003","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786003","url":null,"abstract":"In this paper, we grow and characterize in detail native-oxide-free ultra-thin gate oxide (T/sub ox/=2.4 nm) by an advance clustered vertical furnace with in-situ HF-vapor stripping of the native oxide. Excellent results are demonstrated. Gate oxide integrity is significantly improved in terms of leakage, time-to-breakdown, breakdown field, interface-state-density, stress-induced leakage current, I/sub d/, and G/sub m/. In-situ HF-vapor cleaning by a clustered vertical furnace therefore appears to be very promising to grow high-quality native-oxide-free gate oxide for future deep-submicron device application.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121800957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new design for a 1280/spl times/1024 digital CMOS image sensor with enhanced sensitivity, dynamic range and FPN 新设计的1280/spl倍/1024数字CMOS图像传感器，具有增强的灵敏度、动态范围和FPN
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786043
Jih-Shin Ho, Ming-Cheng Chiang, Han-Min Cheng, Tzu-Ping Lin, M. Kao
{"title":"A new design for a 1280/spl times/1024 digital CMOS image sensor with enhanced sensitivity, dynamic range and FPN","authors":"Jih-Shin Ho, Ming-Cheng Chiang, Han-Min Cheng, Tzu-Ping Lin, M. Kao","doi":"10.1109/VTSA.1999.786043","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786043","url":null,"abstract":"This paper reports a 1.3 M-pixel CMOS image sensor with 5 /spl mu/m/spl times/5 /spl mu/m pixel size fabricated with a standard 0.35 /spl mu/m CMOS logic process. Three techniques have been applied to improve the chip performance: an N-well photodiode to increase the quantum efficiency for light of long wavelengths; two-stage integration to enhance the performance under high illumination conditions; and capacitor-coupled readout to suppress the column Fixed Pattern Noise (FPN). Random access in rows and downsampling in columns are applicable to both B/W and color sensors.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127540970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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