A new design for a 1280/spl times/1024 digital CMOS image sensor with enhanced sensitivity, dynamic range and FPN

Abstract

This paper reports a 1.3 M-pixel CMOS image sensor with 5 /spl mu/m/spl times/5 /spl mu/m pixel size fabricated with a standard 0.35 /spl mu/m CMOS logic process. Three techniques have been applied to improve the chip performance: an N-well photodiode to increase the quantum efficiency for light of long wavelengths; two-stage integration to enhance the performance under high illumination conditions; and capacitor-coupled readout to suppress the column Fixed Pattern Noise (FPN). Random access in rows and downsampling in columns are applicable to both B/W and color sensors.