The conversion of bulk CMOS circuits to SOI technology and its noise impact

Abstract

The faster switching speed and smaller parasitic capacitance of SOI circuits have provided 20% performance improvement over their bulk predecessors, but the characteristics of SOI circuits also introduced significant noise problems that cannot be overlooked. This paper addresses the design issues of remapping bulk CMOS circuits to the SOI technology, and discusses how to minimize the power supply noise by optimizing the placement of on-chip decoupling capacitors.