Design challenges for high-performance SOI digital CMOS VLSI

Abstract

This paper reviews the recent advances of SOI for high-performance digital CMOS VLSI applications. The technology/device requirements and design issues/challenges for high-performance, general-purpose microprocessor applications are differentiated with respect to low-power portable applications. Particular emphasis is placed on the impact of floating-body in partially-depleted devices on the circuit operation, stability, and functionality. Unique SOI design aspects such as the parasitic bipolar effect and hysteretic V/sub T/ variation are addressed. Circuit techniques to improve the noise immunity and global design issues are discussed.