发布求助
文献互助 智能选刊 最新文献

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)最新文献

筛选
英文 中文
The dominant mechanisms of hot-hole injection induced SILC and their correlation with disturbs in N-flash memory cells 热孔注入诱导n -闪存细胞SILC的主要机制及其与扰动的相关性
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.786049
S. Chung, C. Yih, Z. Ho, C. Lin, D. Kuo, M. Liang
{"title":"The dominant mechanisms of hot-hole injection induced SILC and their correlation with disturbs in N-flash memory cells","authors":"S. Chung, C. Yih, Z. Ho, C. Lin, D. Kuo, M. Liang","doi":"10.1109/VTSA.1999.786049","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786049","url":null,"abstract":"In this paper, we have developed a new method for studying the disturb failure mechanisms caused by stress-induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual contributions of carrier charging/discharging in the oxide and the trap-assisted electron tunneling into the floating gate on the threshold voltage shift by using one memory cell only. Results show that, at low oxide field, the main contribution to the disturb is by carrier charging/discharging in the oxide. This disturb is due to the capacitance coupling effect instead of the flat-band voltage shift. At high field, the trap-assisted electron tunneling induced floating-gate charge variation is the major factor of disturb failure.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129521768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of a high speed multiport register file in a 1.8 V, 0.25 /spl mu/m CMOS bulk and SOI technology 在1.8 V, 0.25 /spl mu/m CMOS体和SOI技术中实现高速多端口寄存器文件
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.786053
R. Joshi, W. Hwang, S. Wilson, G. Shahidi, C. Chuang
{"title":"Implementation of a high speed multiport register file in a 1.8 V, 0.25 /spl mu/m CMOS bulk and SOI technology","authors":"R. Joshi, W. Hwang, S. Wilson, G. Shahidi, C. Chuang","doi":"10.1109/VTSA.1999.786053","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786053","url":null,"abstract":"The experimental hardware results of a high speed 8-port, 32 word/spl times/64-bit register file in 1.8 V, 0.25 /spl mu/m CMOS bulk and SOI silicon technology are presented. Such a register file is designed for bulk technology but is also remapped and fabricated in SOI technology without any body contacts. It is shown that the register file in SOI achieves more than 20% performance gain over the counterpart.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126580499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Edge FN stress induced leakage current in tunnel oxides 隧道氧化物中边缘FN应力引起的泄漏电流
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.786050
N. Zous, C. Yeh, C.W. Tsai, L. Chiang, Tahui Wang
{"title":"Edge FN stress induced leakage current in tunnel oxides","authors":"N. Zous, C. Yeh, C.W. Tsai, L. Chiang, Tahui Wang","doi":"10.1109/VTSA.1999.786050","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786050","url":null,"abstract":"The mechanism and characteristics of edge FN stress induced leakage current (SILC) in tunnel oxides are investigated. The dominant SILC mechanism is found to be positive oxide charge assisted electron tunneling. A pronounced transient effect in edge FN SILC is observed. The transient effect arises from the fact that positive oxide charges, which help electrons tunnel through the oxide, can themselves escape to the Si substrate at a positive measurement field. The edge FN SILC can be significantly reduced by using a substrate hot electron injection technique.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121444460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Layout design on bond pads to improve the firmness of bond wire in packaged IC products 为提高封装IC产品中键合线的牢固性，对键合片进行布局设计
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.786022
Jeng-Jie Peng, M. Ker, N. Wang, H. Jiang
{"title":"Layout design on bond pads to improve the firmness of bond wire in packaged IC products","authors":"Jeng-Jie Peng, M. Ker, N. Wang, H. Jiang","doi":"10.1109/VTSA.1999.786022","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786022","url":null,"abstract":"During the manufacture of IC products, the breaking of bond wires or the peeling of bond pads occurs frequently and thus results in the open circuit phenomenon in the IC's. There are several methods proposed to overcome this problem, but additional special process flows are desired for all of these previous methods. This paper presents a layout design method to improve the bond wire reliability in a standard CMOS process. By changing the layout patterns on the bond pads, the firmness of bond wires on the bond pads can be improved. One set of layout patterns on the bond pads has been designed and fabricated in a 0.6 /spl mu/m IP3M CMOS process for the ball shear test and the wire pull test. By implementing the effective layout designs in IC products, the bond wire reliability can be obviously improved in a standard CMOS process.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132292721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An efficient method for the decomposition and resynthesis of speed-independent circuits 一种速度无关电路的有效分解和再合成方法
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.786000
Ren-Der Chen, J. Jou
{"title":"An efficient method for the decomposition and resynthesis of speed-independent circuits","authors":"Ren-Der Chen, J. Jou","doi":"10.1109/VTSA.1999.786000","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786000","url":null,"abstract":"This paper presents a time and area efficient method for the decomposition and resynthesis of speed-independent circuits from the signal transition graph (STG) specification. Our method first investigates the hazard-free decomposition of all high-fanin gates without adding any signals to the original specification. For those gates that can not be hazard-freely decomposed, we propose new signal-adding methods for resynthesis. Our decomposition and resynthesis techniques have been fully automated and applied to several asynchronous benchmarks. Compared with previous work, our method lowers the run time by 1-2 orders of magnitude, and the implementation area is also reduced.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114782794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode VLSI实现的定时恢复和载波恢复为QAM/VSB双模式
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.786024
S. Jou, Chun Hung Kuo, Muh-Tian Shiau, Jung-Yu Heh, Chrong-Kuang Wang
{"title":"VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode","authors":"S. Jou, Chun Hung Kuo, Muh-Tian Shiau, Jung-Yu Heh, Chrong-Kuang Wang","doi":"10.1109/VTSA.1999.786024","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786024","url":null,"abstract":"In this paper, a VLSI implementation of timing recovery (TR) and carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV is introduced. The proposed TR uses a simple baud-rate algorithm and the CR uses decision-directed approach with steep gradient algorithm, which can be used for both QAM and VSB signals. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. Finally, the TR and CR are implemented by TSMC 0.6 /spl mu/m IP3M process. The total gate count is 12985 and the core size is 2175 by 1237 um/sup 2/. It consumes only 7.32 mW when operated at 2 V.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116843802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信