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1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)最新文献

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An ISM-915 MHz RF transceiver IC ism - 915mhz射频收发芯片
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786025
Chien-Kuang Lee, Chia-Huang Wang, Tzu-Yi Yang, Ching-Feng Lee
{"title":"An ISM-915 MHz RF transceiver IC","authors":"Chien-Kuang Lee, Chia-Huang Wang, Tzu-Yi Yang, Ching-Feng Lee","doi":"10.1109/VTSA.1999.786025","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786025","url":null,"abstract":"A high-performance RF transceiver IC for use in ISM-915 MHz application has been designed. It integrates T/R switch, LNA, mixer, and PA into a TSSOP-20/E package. By using this transceiver IC, it is easy to construct a small size and high performance RF module. In Rx-mode, the overall (including filters and T/R switch) noise figure and conversion gain are 3.5 dB and 25 dB, respectively, at 3 V supply voltage. In Tx-mode, it could transmit 21 dBm output power at 3.3 V voltage supply.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125620560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hysteresis in floating-body PD/SOI CMOS circuits 浮体PD/SOI CMOS电路的磁滞
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786054
M. Pelella, C. Chuang, C. Tretz, B. Curran, M. Rosenfield
{"title":"Hysteresis in floating-body PD/SOI CMOS circuits","authors":"M. Pelella, C. Chuang, C. Tretz, B. Curran, M. Rosenfield","doi":"10.1109/VTSA.1999.786054","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786054","url":null,"abstract":"In this paper the hysteretic (history-dependent) propagation gate delay of floating-body (FB) partially depleted (PD) SOI CMOS circuits is investigated. The change in gate propagation delay with time is examined with no preconditioning of the floating-body. The simulation-based analysis includes the sensitivity of the hysteresis to supply voltage, Wp/Wn (beta ratio), duty cycle, slew rate, output load, and initial state of the circuit. Basic physical mechanisms underlying the hysteretic circuit behavior are examined. The results identify the main contributors and general trends of hysteresis in FB PD/SOI circuits. The insight gained can ultimately be incorporated into conventional circuit timing tools. The results also reveal a circuit sizing methodology to minimize the hysteresis effects in circuits using PD/SOI technology.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125830498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Fault detection and location of dynamic reconfigurable FPGAs 动态可重构fpga的故障检测与定位
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786038
Chi-Feng Wu, Cheng-Wen Wu
{"title":"Fault detection and location of dynamic reconfigurable FPGAs","authors":"Chi-Feng Wu, Cheng-Wen Wu","doi":"10.1109/VTSA.1999.786038","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786038","url":null,"abstract":"Dynamic reconfigurable FPGAs provide a platform for reconfigurable computing as well as fast prototyping and emulation. For such FPGAs, we propose a dynamic serial (DS) test approach which takes advantage of their dynamic reconfiguration feature for testing. Compared with the parallel approach, the DS test approach significantly reduces the test configuration time and requires less I/O pins, resulting in a faster and easier testing procedure for dynamic reconfigurable FPGAs.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114905963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Analysis of hot-carrier degradation in 0.25-/spl mu/m surface-channel pMOSFET devices 0.25-/spl mu/m表面沟道pMOSFET器件的热载流子退化分析
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.786005
C.H. Liu, M.G. Chen, S. Huang-Lu, Y.J. Chang, K. Fu
{"title":"Analysis of hot-carrier degradation in 0.25-/spl mu/m surface-channel pMOSFET devices","authors":"C.H. Liu, M.G. Chen, S. Huang-Lu, Y.J. Chang, K. Fu","doi":"10.1109/VTSA.1999.786005","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786005","url":null,"abstract":"Three conventional hot-carrier (HC) stress conditions (i.e. stress at Vgs/spl ap/Vth, Vgs/spl ap/Vds//sup 2/, and Vgs/spl ap/Vds) have been studied for a quarter-micrometer level surface-channel pMOSFET devices. It is shown that stress at Vgs/spl ap/Vth results in the worst-case damage, in which a \"turn-around\" behavior for device parameters (such as Idsat, Vth, and gm) has been observed (this is not seen in 0.35-/spl mu/m or longer p-channel devices to the best of our knowledge). This turnaround behavior could be explained by a two-step degradation model (i.e. electron trapping and charge compensation between electron trapping and interface-state generation). Moreover, similar to long-channel pMOSFET devices though the dominant degradation mechanism is somewhat different, DC device lifetime for 0.25-/spl mu/m pMOSFET devices should be evaluated using gate current as a predictor rather than substrate current that has been suggested by some researchers.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116229961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ultra thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N/sub 2/O oxidation of NH/sub 3/-nitrided Si 采用NH/ sub3 /-氮化硅原位快速热N/ sub2 /O氧化法制备超薄高品质叠氮/氧化栅电介质
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.786004
S.C. Song, H. Luan, C. Lee, A. Mao, S.J. Lee, J. Gelpey, M. Marcus, D. Kwong
{"title":"Ultra thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N/sub 2/O oxidation of NH/sub 3/-nitrided Si","authors":"S.C. Song, H. Luan, C. Lee, A. Mao, S.J. Lee, J. Gelpey, M. Marcus, D. Kwong","doi":"10.1109/VTSA.1999.786004","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786004","url":null,"abstract":"In this paper, we report ultra thin high quality nitride/oxide gate dielectrics prepared by rapid thermal NH/sub 3/ nitridation of Si followed by in-situ N/sub 2/O oxidation (NH/sub 3/+N/sub 2/O process). These films show excellent interface properties, significant lower leakage current (/spl sim/10/sup 2//spl times/), enhanced reliability, and superior boron diffusion barrier properties compared with SiO/sub 2/ of identical thickness.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134362430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low-power multirate IF digital frequency down converter 低功率多速率中频数字下变频
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.786042
S. Jou, Shou-Yang Wu, Chorng-Kuang Wang
{"title":"Low-power multirate IF digital frequency down converter","authors":"S. Jou, Shou-Yang Wu, Chorng-Kuang Wang","doi":"10.1109/VTSA.1999.786042","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786042","url":null,"abstract":"The architectural design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on a multirate algorithm. It can have very low-power dissipation owing to the reduction in hardware complexity and operational frequency. Design application for an IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6 mW when operated at 2 V.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"84 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121925421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Performance enhancement in deep-submicron poly-SiGe-gated CMOS devices 深亚微米多sigge门控CMOS器件的性能增强
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.785988
Wen-Chin Lee, T. King, C. Hu
{"title":"Performance enhancement in deep-submicron poly-SiGe-gated CMOS devices","authors":"Wen-Chin Lee, T. King, C. Hu","doi":"10.1109/VTSA.1999.785988","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785988","url":null,"abstract":"Poly-SiGe- and poly-Si-gated N/PMOS devices with physical channel lengths down to 0.1 /spl mu/m and gate oxide thicknesses down to 25 /spl Aring/ were fabricated. Device performance and reliability were characterized. The poly SiGe-gated NMOS and PMOS devices provide superior current drive due to less gate-depletion effect and higher inversion hole mobility in poly-SiGe-gated devices. In addition, gate oxide integrity in poly-SiGe-gated MOSFET is as good as poly-Si-gated device. Poly-SiGe-gated PMOSFET has better reliability than poly-Si-gated PMOSFET due to reduction of boron penetration.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"53 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123884573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the impact of indium and boron on the Reversed Narrow-Channel Effect (RNCE) in BULK and SOI MOSFETs 铟和硼对体型和SOI型mosfet中反向窄通道效应的影响
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.785992
A. van Meer, J. Lyu, S. Kubicek, S. De Meyer
{"title":"On the impact of indium and boron on the Reversed Narrow-Channel Effect (RNCE) in BULK and SOI MOSFETs","authors":"A. van Meer, J. Lyu, S. Kubicek, S. De Meyer","doi":"10.1109/VTSA.1999.785992","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785992","url":null,"abstract":"For the first time, experimental results are presented on the Reverse Narrow-Channel Effect (RNCE) in SOI and bulk MOSFETs using indium as a channel dopant. The presented results show that devices with an indium channel exhibit the same RNCE as devices with a boron channel, which refers to the same diffusion mechanisms in deep submicron devices.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116339843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A vertical Si/Si/sub 1-x/Ge/sub x/ heterojunction pMOSFET with reduced DIBL sensitivity, using a novel gate dielectric approach 一种垂直Si/Si/sub - 1-x/Ge/sub -x/异质结pMOSFET，采用新型栅极介电方法，降低了DIBL灵敏度
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.785989
P. Verheyen, N. Collaert, M. Caymax, R. Loo, K. De Meyer, M. Van Rossum
{"title":"A vertical Si/Si/sub 1-x/Ge/sub x/ heterojunction pMOSFET with reduced DIBL sensitivity, using a novel gate dielectric approach","authors":"P. Verheyen, N. Collaert, M. Caymax, R. Loo, K. De Meyer, M. Van Rossum","doi":"10.1109/VTSA.1999.785989","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785989","url":null,"abstract":"This paper describes a novel vertical pMOS transistor, based on a Si/Si(1-x)Ge/sub x/ heterojunction at the source/channel interface and using a sacrificial Si layer oxidation as gate dielectric.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134185237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-/spl mu/m silicided process 0.35-/spl μ m硅化工艺下CMOS器件HBM ESD特性的实验研究
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.1999.785993
Tung-Yang Chen, Ming-Dou Ke, Chung-Yu Wu
{"title":"Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-/spl mu/m silicided process","authors":"Tung-Yang Chen, Ming-Dou Ke, Chung-Yu Wu","doi":"10.1109/VTSA.1999.785993","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785993","url":null,"abstract":"In this paper, the layout dependence on ESD robustness of NMOS and PMOS devices in a 0.35-/spl mu/m silicided CMOS process has been experimentally investigated in details. Six 40-pins testchips including 78 different devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.35-/spl mu/m silicided CMOS process to find the optimal layout rules for the ESD protection devices. The gate-driven effect and substrate-triggered effect on the ESD performance of CMOS devices are also measured and compared. The experimental results show that the substrate-triggered effect is much better than the gate-driven effect to improve ESD robustness of the CMOS devices.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114214764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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