Hysteresis in floating-body PD/SOI CMOS circuits

In this paper the hysteretic (history-dependent) propagation gate delay of floating-body (FB) partially depleted (PD) SOI CMOS circuits is investigated. The change in gate propagation delay with time is examined with no preconditioning of the floating-body. The simulation-based analysis includes the sensitivity of the hysteresis to supply voltage, Wp/Wn (beta ratio), duty cycle, slew rate, output load, and initial state of the circuit. Basic physical mechanisms underlying the hysteretic circuit behavior are examined. The results identify the main contributors and general trends of hysteresis in FB PD/SOI circuits. The insight gained can ultimately be incorporated into conventional circuit timing tools. The results also reveal a circuit sizing methodology to minimize the hysteresis effects in circuits using PD/SOI technology.