动态可重构fpga的故障检测与定位

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI:10.1109/VTSA.1999.786038

Chi-Feng Wu, Cheng-Wen Wu

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引用次数: 9

摘要

动态可重构fpga为可重构计算以及快速原型和仿真提供了一个平台。对于此类fpga，我们提出了一种利用其动态重构特性进行测试的动态串行(DS)测试方法。与并行方法相比，DS测试方法显著减少了测试配置时间，所需的I/O引脚更少，从而使动态可重构fpga的测试过程更快、更容易。

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Fault detection and location of dynamic reconfigurable FPGAs

Dynamic reconfigurable FPGAs provide a platform for reconfigurable computing as well as fast prototyping and emulation. For such FPGAs, we propose a dynamic serial (DS) test approach which takes advantage of their dynamic reconfiguration feature for testing. Compared with the parallel approach, the DS test approach significantly reduces the test configuration time and requires less I/O pins, resulting in a faster and easier testing procedure for dynamic reconfigurable FPGAs.

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来源期刊

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

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