低功率多速率中频数字下变频

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI:10.1109/VTSA.1999.786042

S. Jou, Shou-Yang Wu, Chorng-Kuang Wang

{"title":"低功率多速率中频数字下变频","authors":"S. Jou, Shou-Yang Wu, Chorng-Kuang Wang","doi":"10.1109/VTSA.1999.786042","DOIUrl":null,"url":null,"abstract":"The architectural design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on a multirate algorithm. It can have very low-power dissipation owing to the reduction in hardware complexity and operational frequency. Design application for an IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6 mW when operated at 2 V.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"84 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Low-power multirate IF digital frequency down converter\",\"authors\":\"S. Jou, Shou-Yang Wu, Chorng-Kuang Wang\",\"doi\":\"10.1109/VTSA.1999.786042\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The architectural design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on a multirate algorithm. It can have very low-power dissipation owing to the reduction in hardware complexity and operational frequency. Design application for an IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6 mW when operated at 2 V.\",\"PeriodicalId\":237214,\"journal\":{\"name\":\"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)\",\"volume\":\"84 3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTSA.1999.786042\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.1999.786042","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

所提出的中频数字下变频(DFDC)的结构设计是基于多速率算法的4中频过采样和多级插值有限脉冲响应滤波器设计技术的结合。由于降低了硬件复杂性和工作频率，它可以具有非常低的功耗。中频为4.9152 MHz的IS-95 CDMA的设计应用表明，当工作在2 V时，DFDC仅消耗0.6 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Low-power multirate IF digital frequency down converter

The architectural design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on a multirate algorithm. It can have very low-power dissipation owing to the reduction in hardware complexity and operational frequency. Design application for an IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6 mW when operated at 2 V.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

自引率

0.00%

发文量