A vertical Si/Si/sub 1-x/Ge/sub x/ heterojunction pMOSFET with reduced DIBL sensitivity, using a novel gate dielectric approach

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1900-01-01 DOI:10.1109/VTSA.1999.785989

P. Verheyen, N. Collaert, M. Caymax, R. Loo, K. De Meyer, M. Van Rossum

引用次数: 3

Abstract

This paper describes a novel vertical pMOS transistor, based on a Si/Si(1-x)Ge/sub x/ heterojunction at the source/channel interface and using a sacrificial Si layer oxidation as gate dielectric.

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一种垂直Si/Si/sub - 1-x/Ge/sub -x/异质结pMOSFET，采用新型栅极介电方法，降低了DIBL灵敏度

本文描述了一种新型垂直pMOS晶体管，该晶体管基于源/通道接口的Si/Si(1-x)Ge/sub x/异质结，并使用牺牲Si氧化层作为栅极介质。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

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