发布求助
文献互助 智能选刊 最新文献

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)最新文献

筛选
英文 中文
A system level integration methodology for MPEG-2 audio decoder with embedded RISC core 基于嵌入式RISC内核的MPEG-2音频解码器的系统级集成方法
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.785996
T. Tsai, Liang-Gee Chen, R. Wu
{"title":"A system level integration methodology for MPEG-2 audio decoder with embedded RISC core","authors":"T. Tsai, Liang-Gee Chen, R. Wu","doi":"10.1109/VTSA.1999.785996","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785996","url":null,"abstract":"MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. Based on standard cell design technique, the chip size is 6.4/spl times/6.4 mm/sup 2/, and the tested chip can run at maximum 43.5 MHz clock rate.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126335093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel UV baking process to improve DUV photoresist hardness 一种提高UV光刻胶硬度的新型UV烘烤工艺
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786019
C.S. Hunag, B. Tsui, H. Shieh, R. Mohondro
{"title":"A novel UV baking process to improve DUV photoresist hardness","authors":"C.S. Hunag, B. Tsui, H. Shieh, R. Mohondro","doi":"10.1109/VTSA.1999.786019","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786019","url":null,"abstract":"A new baking gas using a mixture of NH/sub 3/ and N/sub 2/ gases can effectively reduce the photoresist thickness shrinkage, CD variation and footing during the UV-bake DUV photoresist hardening process has been developed. After this UV baking process, a higher etch selectivity to photoresist and better CD control and profile processing can be achieved in high density plasma (HDP) dry etchers for applications to 0.2 /spl mu/m contact holes with aspect-ratio greater than 5 and 0.22 /spl mu/m aluminum metal lines with aspect-ratio of 2.5.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130247238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A high-speed built-in-self-test design for DRAMs 一种高速内嵌式dram自检设计
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.785997
Shi-Yu Huang, D. Kwai
{"title":"A high-speed built-in-self-test design for DRAMs","authors":"Shi-Yu Huang, D. Kwai","doi":"10.1109/VTSA.1999.785997","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785997","url":null,"abstract":"A high-speed Built-In Self-Test (BIST) design for Dynamic Random Access Memories (DRAMs) is proposed. The circuit automatically generates a sequence of pre-defined test patterns for on-chip DRAM testing. The innovation herein is mainly an architecture consisting of two finite state machines, instead of the conventional single finite state machine. Based upon this novel architecture, the pipeline technique can then be applied to divide the pattern generation process into stages, leading to a higher-speed design. In addition to pipelining, a technique referred to as protocol-based relaxation is also incorporated. This technique, imposing a certain protocol on the two communicating finite state machines, further relaxes the timing criticality of the design. Synthesis results show that the proposed BIST circuit can operate at the speed of as high as 400 MHz using 0.35 um CMOS technology.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131819630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The reliability of multilevel analog memory in a voice storage and playback system using source-side injection flash 基于源侧注入闪存的语音存储与回放系统中多电平模拟存储器的可靠性
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786051
A.V. Kordesch, S. Awsare, J. Brennan, P. Guo, M. Hemming, M. Herman, P. Holzmann, E. Ng, Chun-Mai Liu, K. Su, C. Wang, M. Wu
{"title":"The reliability of multilevel analog memory in a voice storage and playback system using source-side injection flash","authors":"A.V. Kordesch, S. Awsare, J. Brennan, P. Guo, M. Hemming, M. Herman, P. Holzmann, E. Ng, Chun-Mai Liu, K. Su, C. Wang, M. Wu","doi":"10.1109/VTSA.1999.786051","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786051","url":null,"abstract":"The reliability of a multilevel analog memory is mainly determined by data retention, cycling endurance, and read and write disturb. This storage system retains a voice message for 10 years and can record continuously for 50 K cycles. It can tolerate up to 300 single cell retention shifts >50 mV and still meet THD<0.5% and SINAD>32 dB.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129519331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Gate prespacers for high density DRAMs 用于高密度dram的栅极预垫剂
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786048
R. Divakaruni, M. Weybright, Y. Li, U. Gruening, J. Mandelman, J. Gambino, J. Alsmeier, G. Bronner
{"title":"Gate prespacers for high density DRAMs","authors":"R. Divakaruni, M. Weybright, Y. Li, U. Gruening, J. Mandelman, J. Gambino, J. Alsmeier, G. Bronner","doi":"10.1109/VTSA.1999.786048","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786048","url":null,"abstract":"The channel length of the DRAM transfer gate device continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for the low leakage DRAM transfer device. There is thus a need for novel integration schemes that allow the continued cell shrinkage with only limited shrinking of the channel length. In this paper, we present an integration scheme which allows for a larger gate polysilicon length for a given pitch thus improving array device leakage (by about one generation) for a given technology.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116304311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low-voltage analog CMOS circuit techniques 低压模拟CMOS电路技术
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786056
J. Fattaruso
{"title":"Low-voltage analog CMOS circuit techniques","authors":"J. Fattaruso","doi":"10.1109/VTSA.1999.786056","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786056","url":null,"abstract":"As power supply voltages are driven down by digital power constraints, circuit techniques must evolve to preserve the precision of analog functions in a mixed-signal system. This paper reviews recent developments in low-voltage CMOS design of opamps and other critical analog blocks where high gain and signal-to-noise ratio are required.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"350 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122338270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A trap generation statistical model in closed-form for intrinsic breakdown of ultra-thin oxides 超薄氧化物本征击穿的闭式陷阱生成统计模型
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786002
Huan-Tsung Huang, Ming-Jer Chen, Jyh-Huei Chen, C. Su, C. Hou, M. Liang
{"title":"A trap generation statistical model in closed-form for intrinsic breakdown of ultra-thin oxides","authors":"Huan-Tsung Huang, Ming-Jer Chen, Jyh-Huei Chen, C. Su, C. Hou, M. Liang","doi":"10.1109/VTSA.1999.786002","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786002","url":null,"abstract":"A trap generation statistical model with the trap radius r and the trap filling fraction p both as parameters has been formulated in closed-form for intrinsic breakdown of ultra-thin oxides. Reproduction of experimental Q/sub BD/ distributions for different oxide thicknesses and areas has been achieved through the model. The extracted values of r and p are quite comparable with the literature ones. The model itself has successfully predicted the ultimate thickness limit for breakdown. Also presented is the Emission Spectroscopy (EMMI) of breakdown sites as well as Atomic Force Microscope (AFM) images of silicon and oxide surfaces, to validate the assumptions used in model.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122449657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Embedded flash memories-technology assessment and future 嵌入式闪存-技术评估与未来
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786030
K. Yoshikawa
{"title":"Embedded flash memories-technology assessment and future","authors":"K. Yoshikawa","doi":"10.1109/VTSA.1999.786030","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786030","url":null,"abstract":"While embedded flash technologies should be the key for the next decade system-on-a-chip, current aggressive scaling of logic CMOS devices increases the difficulty for the cost effective device realization. Various approaches and requirements for embedded flash devices will be discussed from broad viewpoints, such as device physics, process integration and reliability. Future ideal cell structure will also be addressed.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122151973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
CMOS scaling beyond 0.1 /spl mu/m: how far can it go? CMOS缩放超过0.1 /spl mu/m:能走多远?
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.785986
Y. Taur
{"title":"CMOS scaling beyond 0.1 /spl mu/m: how far can it go?","authors":"Y. Taur","doi":"10.1109/VTSA.1999.785986","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785986","url":null,"abstract":"This paper discusses the issues, challenges, and possible directions for further scaling and performance gains beyond 0.1 /spl mu/m CMOS. Gate oxides, already down to a few atomic layers thick, will soon be limited by tunneling currents to a thickness of 15-20 /spl Aring/. A general guideline, based on 2-D effects in MOSFETs, is given for the length scaling of high-k gate dielectrics. A feasible design for 25 mm bulk CMOS is to use a highly abrupt, vertically and laterally nonuniform doping profile to control the short-channel effect. The effect of polysilicon-gate depletion on the performance of 25 nm CMOS is examined and quantified. Beyond conventional CMOS, the question whether any of the exploratory device structures, including ultra-thin SOI and double-gate MOSFET, can extend CMOS scaling to 10 nm channel length is addressed.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122252693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
CMP of polyimide for low-k dielectric application in ULSI 低k介电介质应用于ULSI的聚酰亚胺CMP
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786020
Y. Tai, B. Dai, M. Tsai, I. Tung, M. Feng
{"title":"CMP of polyimide for low-k dielectric application in ULSI","authors":"Y. Tai, B. Dai, M. Tsai, I. Tung, M. Feng","doi":"10.1109/VTSA.1999.786020","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786020","url":null,"abstract":"Polyimide CMP is investigated for its feasibility in IMD planarization applications. The polish rates of polyimide are found to be heavily dependent upon the degree of imidization and hydroxyl activity in silica-based alkaline slurry. TMAH, tetra-methyl-ammonium hydroxide, added into the slurry enhances the removal rate of polyimide due to the improved wettability on the hydrophobic polyimide surface. Surface planarity is degraded during CMP, but can be significantly improved by a curing after CMP. By means of bias-temperature-stress analysis, it is found that mobile ions, like K/sup +/ and Na/sup +/, do not diffuse into the bulk of the polished film. Dielectric constant and leakage current density of polyimide being polished do not deteriorate, indicating polyimide directly capped with an oxide layer is promising for use as IMDs.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"647 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131826025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信