A high-speed built-in-self-test design for DRAMs

Abstract

A high-speed Built-In Self-Test (BIST) design for Dynamic Random Access Memories (DRAMs) is proposed. The circuit automatically generates a sequence of pre-defined test patterns for on-chip DRAM testing. The innovation herein is mainly an architecture consisting of two finite state machines, instead of the conventional single finite state machine. Based upon this novel architecture, the pipeline technique can then be applied to divide the pattern generation process into stages, leading to a higher-speed design. In addition to pipelining, a technique referred to as protocol-based relaxation is also incorporated. This technique, imposing a certain protocol on the two communicating finite state machines, further relaxes the timing criticality of the design. Synthesis results show that the proposed BIST circuit can operate at the speed of as high as 400 MHz using 0.35 um CMOS technology.