CMOS scaling beyond 0.1 /spl mu/m: how far can it go?

Abstract

This paper discusses the issues, challenges, and possible directions for further scaling and performance gains beyond 0.1 /spl mu/m CMOS. Gate oxides, already down to a few atomic layers thick, will soon be limited by tunneling currents to a thickness of 15-20 /spl Aring/. A general guideline, based on 2-D effects in MOSFETs, is given for the length scaling of high-k gate dielectrics. A feasible design for 25 mm bulk CMOS is to use a highly abrupt, vertically and laterally nonuniform doping profile to control the short-channel effect. The effect of polysilicon-gate depletion on the performance of 25 nm CMOS is examined and quantified. Beyond conventional CMOS, the question whether any of the exploratory device structures, including ultra-thin SOI and double-gate MOSFET, can extend CMOS scaling to 10 nm channel length is addressed.