The dominant mechanisms of hot-hole injection induced SILC and their correlation with disturbs in N-flash memory cells

Abstract

In this paper, we have developed a new method for studying the disturb failure mechanisms caused by stress-induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual contributions of carrier charging/discharging in the oxide and the trap-assisted electron tunneling into the floating gate on the threshold voltage shift by using one memory cell only. Results show that, at low oxide field, the main contribution to the disturb is by carrier charging/discharging in the oxide. This disturb is due to the capacitance coupling effect instead of the flat-band voltage shift. At high field, the trap-assisted electron tunneling induced floating-gate charge variation is the major factor of disturb failure.