VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode

Abstract

In this paper, a VLSI implementation of timing recovery (TR) and carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV is introduced. The proposed TR uses a simple baud-rate algorithm and the CR uses decision-directed approach with steep gradient algorithm, which can be used for both QAM and VSB signals. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. Finally, the TR and CR are implemented by TSMC 0.6 /spl mu/m IP3M process. The total gate count is 12985 and the core size is 2175 by 1237 um/sup 2/. It consumes only 7.32 mW when operated at 2 V.