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1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)最新文献

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Wireless transceivers in CMOS IC technology. The new wave 采用CMOS集成电路技术的无线收发器。新浪潮
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786023
A. Abidi
{"title":"Wireless transceivers in CMOS IC technology. The new wave","authors":"A. Abidi","doi":"10.1109/VTSA.1999.786023","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786023","url":null,"abstract":"Starting from a topic initially confined to academic research the field of RF-CMOS integrated circuits has now progressed to the point that it is on the threshold of important commercial deployment. Progress is on several fronts. New MOS-appropriate circuit techniques have been discovered for many of the RF, IF and baseband blocks required in state-of-the-art wireless transceivers. Transceiver architectures have evolved to take advantage of the strengths of CMOS, and to circumvent its weaknesses. Recent CMOS implementations of RF and IF blocks combine analog circuits with switched and digital functions in unprecedented ways. The object of this paper is to summarize the important concepts underlying good practice in the design of RF-CMOS circuits, and the experience to date in integrating transceivers.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128238932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
On the cell misalignment for multilevel storage FLASH E/sup 2/PROM 关于多级存储FLASH /sup /PROM的单元错位问题
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786032
C. Wang, M. Hemming, P. Klinger, A.V. Kordesch, Chun-Mai Liu, K. Su
{"title":"On the cell misalignment for multilevel storage FLASH E/sup 2/PROM","authors":"C. Wang, M. Hemming, P. Klinger, A.V. Kordesch, Chun-Mai Liu, K. Su","doi":"10.1109/VTSA.1999.786032","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786032","url":null,"abstract":"This paper presents for the first time the manufacturing issues due to cell misalignment encountered in multilevel FLASH memories. Split gate memory cells in mirrored pairs show varied program efficiency upon less ideal alignment, where device with a shorter Lsg has a poorer efficiency. This misalignment adversely impacts the dynamic range of the storage levels.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"114 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131776633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A case for a multitrace cluster 多迹集群的案例
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.785995
Y. Wu, J. Ling, W. Helms
{"title":"A case for a multitrace cluster","authors":"Y. Wu, J. Ling, W. Helms","doi":"10.1109/VTSA.1999.785995","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785995","url":null,"abstract":"The ability to place vast transistor count on a single chip offers designers to experiment with a new architecture. A new architecture alternatives, known as Mulitrace Cluster, is proposed to overcome the limits of circuit technology and microarchitecture.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132734441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 16-minute 3-V analog storage and retrieval integrated circuit system using source-side injection flash technology 一个16分钟的3-V模拟存储和检索集成电路系统，采用源侧注入闪存技术
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786058
J. Brennan, S. Awsare, T. Dunne, M. Hemming, P. Holzmann, G. Jackson, A.V. Kordesch, Chun-Mai Liu, K. Su, H. Tran
{"title":"A 16-minute 3-V analog storage and retrieval integrated circuit system using source-side injection flash technology","authors":"J. Brennan, S. Awsare, T. Dunne, M. Hemming, P. Holzmann, G. Jackson, A.V. Kordesch, Chun-Mai Liu, K. Su, H. Tran","doi":"10.1109/VTSA.1999.786058","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786058","url":null,"abstract":"A single-chip 3 V analog storage and retrieval system is reported utilizing source-side injection flash. It records 16 minutes of audio signals, at a sampling rate of 4 kHz, in a 4 Mb flash array with a resolution approaching 8-bit. The die size is 4.2/spl times/9.8 mm/sup 2/ and cell size is 4 /spl mu/m/sup 2/.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131659146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An efficient architecture for two-dimensional discrete wavelet transform 二维离散小波变换的高效结构
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786013
Po-Cheng Wu, Liang-Gee Chen
{"title":"An efficient architecture for two-dimensional discrete wavelet transform","authors":"Po-Cheng Wu, Liang-Gee Chen","doi":"10.1109/VTSA.1999.786013","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786013","url":null,"abstract":"This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer. In the transform-module, we employ the polyphase decomposition technique to the decimation filters of stage 1, and the coefficient folding technique to the decimation filters of stage 2. The RAM size is N/2/spl times/N/2. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are the near 100% hardware utilization, fast computation time, regular data flow, and low complexity control circuit, making this architecture suitable for next generation image compression systems.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115770618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 201
ASET activities toward the 21st century 面向21世纪的ASET活动
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.785984
A. Ishitani
{"title":"ASET activities toward the 21st century","authors":"A. Ishitani","doi":"10.1109/VTSA.1999.785984","DOIUrl":"https://doi.org/10.1109/VTSA.1999.785984","url":null,"abstract":"ASET is a Japanese electronics research and development (R&D) consortium, and founded to innovate technology infrastructure for the 21st century. Firstly, MITI prepared this project, and asked NEDO for implementing this project. MITI is Ministry of International Trade and Industry, and NEDO is New Energy and Industrial Technology Development organization. NEDO informed this project to industry. Industry submitted application forms to NEDO. Qualified companies by NEDO organized ASET. ASET has 36 member companies. Of the 36, 18 companies are involved in semiconductor R&D of ASET.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121014568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New divided-source structure to eliminate instability of threshold voltage in p-channel flash memory using channel hot-hole-induced-hot-electron programming 采用通道热孔感应热电子编程的新型分源结构消除p通道闪存中阈值电压的不稳定性
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786035
F. Lin, C. Hsu
{"title":"New divided-source structure to eliminate instability of threshold voltage in p-channel flash memory using channel hot-hole-induced-hot-electron programming","authors":"F. Lin, C. Hsu","doi":"10.1109/VTSA.1999.786035","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786035","url":null,"abstract":"A divided source structure for p-channel flash memory is introduced to eliminate the threshold voltage instability during operation. The instability comes from the strong hot electron gate current of unselected cells having been programmed. The unselected cells will suffer from undesired programming, which creates an undesired leakage of unselected cells during the read operation. The proposed structure enables the source of unselected cells to be raised up to -3 V, which inhibits the channel hot electron generation efficiently due to reduction of the lateral field. Thus stability of the threshold voltage is achieved.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121031040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Polygonal routing network for FPGA/FPIC 用于FPGA/FPIC的多边形路由网络
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786011
Mao-Hsu Yen, Mon-Chau Shie, S. Lan
{"title":"Polygonal routing network for FPGA/FPIC","authors":"Mao-Hsu Yen, Mon-Chau Shie, S. Lan","doi":"10.1109/VTSA.1999.786011","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786011","url":null,"abstract":"The programmable routing network of Field Programmable Gate Array (FPGA) and Field Programmable Interconnection Chip (FPGA) affects its performance, die size, and routability. This paper proposes a polygonal routing network that consists of polygonal switch modules and many rectangular connection modules. For a logic module with 2n pins, the number of switches used in the polygonal routing module is less than the conventional routing module by O(/spl radic/n).","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122608679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A multilevel analog storage memory using source-side injection flash array 一种采用源端注入闪存阵列的多级模拟存储存储器
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786031
Chun-Mai Liu, J. Brennan, P. Guo, P. Holzmann, P. Klinger, A.V. Kordesch, M. Kwan, I-Sheng Liu, K. Su, C. Wang, Hai Wang, Sukyoon Yoon
{"title":"A multilevel analog storage memory using source-side injection flash array","authors":"Chun-Mai Liu, J. Brennan, P. Guo, P. Holzmann, P. Klinger, A.V. Kordesch, M. Kwan, I-Sheng Liu, K. Su, C. Wang, Hai Wang, Sukyoon Yoon","doi":"10.1109/VTSA.1999.786031","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786031","url":null,"abstract":"A multilevel storage technology with resolution approaching 8-bits is developed for storing analog signals directly into a memory array of source-side injection flash EEPROM. This is achieved by devising a read and programming scheme, by optimizing a memory cell layout, and by integrating mixed-mode capabilities into the base digital flash process.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121570585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Whole-chip ESD protection strategy for CMOS IC's with multiple mixed-voltage power pins 多混压电源引脚CMOS集成电路的全片ESD保护策略
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI: 10.1109/VTSA.1999.786059
M. Ker, Hun-Hsien Chang
{"title":"Whole-chip ESD protection strategy for CMOS IC's with multiple mixed-voltage power pins","authors":"M. Ker, Hun-Hsien Chang","doi":"10.1109/VTSA.1999.786059","DOIUrl":"https://doi.org/10.1109/VTSA.1999.786059","url":null,"abstract":"A novel whole-chip ESD (electrostatic discharge) protection design with multiple ESD buses has been proposed to solve the ESD protection issue in CMOS ICs with multiple mixed-voltage power pins. The ESD current in the CMOS IC is diverted into the ESD buses, therefore the ESD current is conducted by the ESD buses away from the internal circuits and quickly discharged through the desired ESD protection devices. By using the ESD buses, the CMOS IC with separated power pins can be safely protected against ESD damage which is often located in the internal circuits.","PeriodicalId":237214,"journal":{"name":"1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131307470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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