Whole-chip ESD protection strategy for CMOS IC's with multiple mixed-voltage power pins

Abstract

A novel whole-chip ESD (electrostatic discharge) protection design with multiple ESD buses has been proposed to solve the ESD protection issue in CMOS ICs with multiple mixed-voltage power pins. The ESD current in the CMOS IC is diverted into the ESD buses, therefore the ESD current is conducted by the ESD buses away from the internal circuits and quickly discharged through the desired ESD protection devices. By using the ESD buses, the CMOS IC with separated power pins can be safely protected against ESD damage which is often located in the internal circuits.