On the cell misalignment for multilevel storage FLASH E/sup 2/PROM

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI:10.1109/VTSA.1999.786032

C. Wang, M. Hemming, P. Klinger, A.V. Kordesch, Chun-Mai Liu, K. Su

引用次数: 3

Abstract

This paper presents for the first time the manufacturing issues due to cell misalignment encountered in multilevel FLASH memories. Split gate memory cells in mirrored pairs show varied program efficiency upon less ideal alignment, where device with a shorter Lsg has a poorer efficiency. This misalignment adversely impacts the dynamic range of the storage levels.

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关于多级存储FLASH /sup /PROM的单元错位问题

本文首次提出了在多电平闪存中由于单元错位而引起的制造问题。镜像对中的分门存储单元在不太理想的对齐时显示出不同的程序效率，其中具有较短Lsg的器件具有较差的效率。这种不对齐对存储水平的动态范围产生不利影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

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