高速VLSI实现的低复杂度序列估计算法及其在千兆以太网1000Base-T中的应用

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) Pub Date : 1999-06-08 DOI:10.1109/VTSA.1999.786027

E. Haratsch

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引用次数: 10

摘要

本文从信噪比性能、VLSI实现、硬件复杂度和关键路径等方面比较了降低复杂度序列估计(RCSE)算法。提出了一种新的结构，降低了RCSE的硬件复杂度，缓解了关键路径问题。该体系结构可用于实现千兆以太网1000Base-T的RCSE。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High-speed VLSI implementation of reduced complexity sequence estimation algorithms with application to Gigabit Ethernet 1000Base-T

This paper compares reduced complexity sequence estimation (RCSE) algorithms in terms of SNR performance, VLSI implementation, hardware complexity and critical path. A novel architecture is presented which reduces the hardware complexity of RCSE and relaxes the critical path problem. This architecture can be used to implement RCSE for Gigabit Ethernet 1000Base-T.

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来源期刊

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

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